參數(shù)資料
型號(hào): CS4351-DZZ
廠商: Cirrus Logic Inc
文件頁(yè)數(shù): 17/37頁(yè)
文件大?。?/td> 0K
描述: IC DAC STER 112DB 192KHZ 20TSSOP
標(biāo)準(zhǔn)包裝: 74
位數(shù): 24
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
功率耗散(最大): 354mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 托盤
輸出數(shù)目和類型: 2 電壓,單極
采樣率(每秒): 192k
配用: 598-1152-ND - BOARD EVAL FOR CS4351 DAC
24
DS566F1
CS4351
6. REGISTER DESCRIPTION
** All register access is R/W unless specified otherwise**
6.1
Chip ID - Register 01h
Function:
This register is Read-Only. Bits 7 through 3 are the part number ID which is 11111b and the remaining Bits
(2 through 0) are for the chip revision (Rev. A = 000, Rev. B = 001, ...)
6.2
Mode Control 1 - Register 02h
6.2.1
Digital Interface Format (DIF2:0) Bits 6-4
Function:
These bits select the interface format for the serial audio input.
The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital
Interface Format and the options are detailed in Figures 5 through 7.
6.2.2
De-Emphasis Control (DEM1:0) Bits 3-2.
Default = 0
00 - No De-emphasis
01 - 44.1 kHz De-emphasis
10 - 48 kHz De-emphasis
11 - 32 kHz De-emphasis
Function:
Selects the appropriate digital filter to maintain the stan-
dard 15
s/50 s digital de-emphasis filter response at
32, 44.1 or 48 kHz sample rates. (See Figure 11.)
Note:
De-emphasis is only available in Single-Speed Mode
76
543
21
0
PART4
PART3
PART2
PART1
PART0
REV2
REV1
REV0
11
111
-
76
543
21
0
Reserved
DIF2
DIF1
DIF0
DEM1
DEM0
FM1
FM0
00
000
00
0
DIF2
DIF1
DIF0
DESCRIPTION
Format
FIGURE
000
Left Justified, up to 24-bit data
0
(Default)
001
I2S, up to 24-bit data
1
010
Right Justified, 16-bit data
2
011
Right Justified, 24-bit data
3
100
Right Justified, 20-bit data
4
101
Right Justified, 18-bit data
5
110
Reserved
111
Reserved
Table 7. Digital Interface Formats
Figure 11. De-Emphasis Curve
Gain
dB
-10dB
0dB
Frequency
T2 = 15 s
T1=50 s
F1
F2
3.183 kHz
10.61 kHz
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