參數(shù)資料
型號(hào): CS4351-DZZ
廠商: Cirrus Logic Inc
文件頁(yè)數(shù): 24/37頁(yè)
文件大?。?/td> 0K
描述: IC DAC STER 112DB 192KHZ 20TSSOP
標(biāo)準(zhǔn)包裝: 74
位數(shù): 24
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
功率耗散(最大): 354mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 托盤
輸出數(shù)目和類型: 2 電壓,單極
采樣率(每秒): 192k
配用: 598-1152-ND - BOARD EVAL FOR CS4351 DAC
30
DS566F1
CS4351
6.7.1
Power Down (PDN) Bit 7
Function:
When set to 1 (default), the entire device will enter a low-power state and the contents of the control reg-
isters will be retained. The power-down bit defaults to ‘1’ on power-up and must be disabled before normal
operation in Control Port mode can occur. This bit is ignored if CPEN is not set.
6.7.2
Control Port Enable (CPEN) Bit 6
Function:
This bit is set to 0 by default, allowing the device to power-up in Stand-Alone Mode. Control Port Mode
can be accessed by setting this bit to 1. This will allow operation of the device to be controlled by the reg-
isters and the pin definitions will conform to Control Port Mode.
6.7.3
Freeze Controls (Freeze) Bit 5
Function:
When set to 1, this function allows modifications to be made to the registers without the changes taking
effect until FREEZE is set back to 0. To make multiple changes in the Control Port registers take effect
simultaneously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit.
When set to 0 (default), register changes take effect immediately.
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