參數(shù)資料
型號(hào): CS4205-KQZ
廠商: Cirrus Logic Inc
文件頁數(shù): 54/81頁
文件大小: 0K
描述: IC CODEC AC97 I2S 48-LQFP
標(biāo)準(zhǔn)包裝: 250
類型: 音頻編解碼器 '97
數(shù)據(jù)接口: 串行
分辨率(位): 18,20 b
ADC / DAC 數(shù)量: 1 / 2
三角積分調(diào)變:
動(dòng)態(tài)范圍,標(biāo)準(zhǔn) ADC / DAC (db): 90 / 90
電壓 - 電源,模擬: 4.75 V ~ 5.25 V
電壓 - 電源,數(shù)字: 4.75 V ~ 5.25 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(9x9)
包裝: 托盤
產(chǎn)品目錄頁面: 754 (CN2011-ZH PDF)
其它名稱: 598-1182
CS4205
58
DS489PP4
8. SONY/PHILIPS DIGITAL
INTERFACE (S/PDIF)
The S/PDIF digital output is used to interface the
CS4205 to consumer audio equipment external to
the PC. This output provides an interface for stor-
ing digital audio data or playing digital audio data
to digital speakers. Figure 22 illustrates the circuits
necessary for implementing the IEC-958 optical or
consumer interface. For further information on
S/PDIF operation see application note AN22: Over-
view of Digital Audio Interface Data Structures [3].
For further information on S/PDIF recommended
transformers see application note AN134: AES and
S/PDIF Recommended Transformers [4].
9. EXCLUSIVE FUNCTIONS
Some of the digital pins on the CS4205 have mul-
tiplexed functionality. These functions are mutual-
ly exclusive and cannot be requested at the same
time. The following pairs of functions are mutually
exclusive:
GPIO and Serial Data Port (GPIO0 pin is
shared with LRCLK pin, GPIO1 pin is shared
with SDOUT pin, and GPIO[4:2] pins are
shared with SDI[3:1] pins)
EAPD and Serial Data Port Serial Clock
(EAPD pin is shared with SCLK pin)
S/PDIF and Second Serial Data Port (SPDO pin
is shared with SDO2 pin)
Use of the GPIO0/LRCLK, GPIO1/SDOUT, and
GPIO[4:2]/SDI[3:1] pins for serial data port has
priority over their GPIO functionality. There is no
priority assigned to the other two exclusive func-
tions. A function currently in use must be disabled
or powered down before the corresponding exclu-
sive function can be enabled. The following control
bits for these functions will behave differently than
normal bits: the EAPD bit in the Powerdown Con-
the SPEN bit in the S/PDIF Control Register (Index
68h), and the SDI[3:1], SDO2, and SDSC bits in
bits can become read-only bits if they control a fea-
ture that is currently unavailable because the corre-
sponding exclusive feature is already in use, or the
corresponding master control for this feature is not
set.
1
2
3
4
5
6
0.1
F
R
2
R
1
J1
DGND
DVdd
R
1
R
2
SPDO/SDO2
S/PDIF_OUT
TOTX-173
SPDO/SDO2
+5V_PCI
DGND
8.2 k
DGND
3.3V
247.5
107.6
5V
375
93.75
T
1
Figure 22. S/PDIF Output
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