參數(shù)資料
型號: CS4270-DZZ
廠商: Cirrus Logic Inc
文件頁數(shù): 1/1頁
文件大?。?/td> 0K
描述: IC CODEC 24BIT 105DB 24TSSOP
標準包裝: 62
類型: 立體聲音頻
數(shù)據(jù)接口: 串行
分辨率(位): 24 b
ADC / DAC 數(shù)量: 2 / 2
三角積分調(diào)變:
動態(tài)范圍,標準 ADC / DAC (db): 105 / 105
電壓 - 電源,模擬: 3.1 V ~ 5.25 V
電壓 - 電源,數(shù)字: 3.1 V ~ 5.25 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 24-TSSOP
包裝: 管件
產(chǎn)品目錄頁面: 754 (CN2011-ZH PDF)
配用: 598-1002-ND - BOARD EVAL FOR CS4270 CODEC
其它名稱: 598-1622
Copyright
Cirrus Logic, Inc. 2006
(All Rights Reserved)
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find the one nearest you, go to http://www.cirrus.com
Errata: CS4270 Rev C0 Silicon
Reference CS4270 Data Sheet DS686PP1
Measured DAC THD+N (0 dB) with VA = 5 V or 3.3 V (nominal voltage) could be -81 dB and does not
meet the -83 dB maximum specification in the Data Sheet. Measured DAC THD+N (0 dB) with VA =
3.0 V (3.3 V min.) is -79 dB and does not meet the -83 dB maximum specification in the Data Sheet.
The digital portions of the part (both ADC and DAC) will not function when MCLK divide by 1.5 is
selected and VD = 3.3 V. The following start-up sequences will correct the problem.
I
n Control Port Mode:
Power-up the part
Hold MCLK Static
Hard reset the part
–Set PDN
Set the Ratio Select bits in Reg. 03h
Release PDN
In Stand-Alone Mode:
Power-up the part
Hold the part in reset
Set the MDIV1,2 pin logic levels
Release reset
AUGUST '06
ER686B2
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