compliant with the Intel
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參數資料
型號: CS4205-KQZ
廠商: Cirrus Logic Inc
文件頁數: 5/81頁
文件大小: 0K
描述: IC CODEC AC97 I2S 48-LQFP
標準包裝: 250
類型: 音頻編解碼器 '97
數據接口: 串行
分辨率(位): 18,20 b
ADC / DAC 數量: 1 / 2
三角積分調變:
動態(tài)范圍,標準 ADC / DAC (db): 90 / 90
電壓 - 電源,模擬: 4.75 V ~ 5.25 V
電壓 - 電源,數字: 4.75 V ~ 5.25 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應商設備封裝: 48-TQFP(9x9)
包裝: 托盤
產品目錄頁面: 754 (CN2011-ZH PDF)
其它名稱: 598-1182
CS4205
DS489PP4
13
2. GENERAL DESCRIPTION
The CS4205 is a mixed-signal serial audio codec
compliant with the Intel Audio Codec ’97 Specifi-
cation, revision 2.1 [6] (referred to as AC ’97). It is
designed to be paired with a digital controller, typ-
ically located on the PCI bus or integrated within
the system core logic chip set. The controller is re-
sponsible for all communications between the
CS4205 and the remainder of the system. The
CS4205 contains two distinct functional sections:
digital and analog. The digital section includes the
AC-link interface, S/PDIF interface, serial data
port, GPIO, signal processing engine, ZV Port,
power management support, and Sample Rate Con-
verters (SRCs). The analog section includes the an-
alog input multiplexer (mux), stereo input mixer,
stereo output mixer, mono output mixer, stereo An-
alog-to-Digital Converters (ADCs), stereo Digi-
tal-to-Analog Converters (DACs), dedicated mono
microphone ADC, and their associated volume
controls.
2.1
AC-Link
All communication with the CS4205 is established
with a 5-wire digital interface to the controller
called the AC-link. This interface is shown in
Figure 7. All clocking for the serial communication
is synchronous to the BIT_CLK signal. BIT_CLK
is generated by the primary audio codec and is used
to clock the controller and any secondary audio co-
decs. Both input and output AC-link audio frames
are organized as a sequence of 256 serial bits form-
ing 13 groups referred to as ‘slots’. During each au-
dio frame, data is passed bi-directionally between
the CS4205 and the controller. The input frame is
driven from the CS4205 on the SDATA_IN line.
The output frame is driven from the controller on
the SDATA_OUT line. The controller is also re-
sponsible for issuing reset commands via the RE-
SET# signal. Following a Cold Reset, the CS4205
is responsible for notifying the controller that it is
ready for operation after synchronizing its internal
functions. The CS4205 AC-link signals must use
the same digital supply voltage as the controller, ei-
ther +5 V or +3.3 V. See Section 4, AC-Link Frame
Definition, for detailed AC-link information.
CODEC
SYNC
BIT_CLK
SDATA_OUT
SDATA_IN
RESET#
Digital AC'97
Controller
AC'97
Figure 7. AC-link Connections
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