
MICROWIRE/PLUS (Continued)
Memory Map
All RAM, ports and registers (except A and PC) are mapped into data memory address space.
Address
Contents
S/ADD REG
0000 to 006F
On-Chip RAM bytes (112 bytes)
0070 to 007F
Unused RAM Address Space (Reads As
All Ones)
xx80 to xx93
Unused RAM Address Space (Reads
Undefined Data)
xx94
Port F data register, PORTFD
xx95
Port F configuration register, PORTFC
xx96
Port F input pins (read only), PORTFP
xx97 to xxAF
Unused address space (Reads
Undefined Data)
xxB0
Timer T3 Lower Byte
xxB1
Timer T3 Upper Byte
xxB2
Timer T3 Autoload Register T3RA Lower
Byte
xxB3
Timer T3 Autoload Register T3RA Upper
Byte
xxB4
Timer T3 Autoload Register T3RB Lower
Byte
xxB5
Timer T3 Autoload Register T3RB Upper
Byte
xxB6
Timer T3 Control Register
xxB7
Comparator Select Register
(Reg:CMPSL)
xxB8
UART Transmit Buffer (Reg:TBUF)
xxB9
UART Receive Buffer (Reg:RBUF)
xxBA
UART Control and Status Register
(Reg:ENU)
xxBB
UART Receive Control and Status
Register (Reg:ENUR)
Address
Contents
S/ADD REG
xxBC
UART Interrupt and Clock Source
Register (Reg:ENUI)
xxBD
UART Baud Register (Reg:BAUD)
xxBE
UART Prescale Select Register
(Reg:PSR)
xxBF
Reserved for UART
xxC0
Timer T2 Lower Byte
xxC1
Timer T2 Upper Byte
xxC2
Timer T2 Autoload Register T2RA Lower
Byte
xxC3
Timer T2 Autoload Register T2RA Upper
Byte
xxC4
Timer T2 Autoload Register T2RB Lower
Byte
xxC5
Timer T2 Autoload Register T2RB Upper
Byte
xxC6
Timer T2 Control Register
xxC7
WATCHDOG Service Register
(Reg:WDSVR)
xxC8
MIWU Edge Select Register
(Reg:WKEDG)
xxC9
MIWU Enable Register (Reg:WKEN)
xxCA
MIWU Pending Register (Reg:WKPND)
xxCB to xxCF
Reserved
xxD0
Port L Data Register
xxD1
Port L Configuration Register
xxD2
Port L Input Pins (Read Only)
xxD3
Reserved for Port L
xxD4
Port G Data Register
xxD5
Port G Configuration Register
DS012829-20
FIGURE 20. MICROWIRE/PLUS Application
COP888xG/CS
Family
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