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參數(shù)資料
| 型號： | COPCSH984XXX/WM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 25/60頁 |
| 文件大小： | 693K |
| 代理商： | COPCSH984XXX/WM |
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Comparators (Continued)
I2
Comparator1 positive input
I1
Comparator1 negative input
Only Comparator 1 is available on the CS series.
A Comparator Select Register (CMPSL) is used to enable
the comparators, read the outputs of the comparators inter-
nally, and enable the outputs of the comparators to the pins.
Two control bits (enable and output enable) and one result
bit are associated with each comparator. The comparator re-
sult bits (CMP1RD and CMP2RD) are read only bits which
will read as zero if the associated comparator is not enabled.
The Comparator Select Register is cleared with reset, result-
ing in the comparators being disabled. The comparators
should also be disabled before entering either the HALT or
IDLE modes in order to save power. The configuration of the
CMPSL register is as follows:
CMPSL REGISTER (ADDRESS X’00B7)
Reserved
CMP20E
CMP2RD
CMP2EN
CMP10E
CMP1RD
CMP1EN
Reserved
Bit 7
Bit 0
The CMPSL register contains the following bits:
Reserved These bits are reserved and must be zero
CMP20E
Selects pin I6 as comparator 2 output provided
that CMP2EN is set to enable the comparator
CMP2RD Comparator 2 result (this is a read only bit, which
will read as 0 if the comparator is not enabled)
CMP2EN
Enable comparator 2
CMP10E
Selects pin I3 as comparator 1 output provided
that CMPIEN is set to enable the comparator
CMP1RD Comparator 1 result (this is a read only bit, which
will read as 0 if the comparator is not enabled)
CMP1EN
Enable comparator 1
Note: For compatibility with existing code and with existing Mask ROMMed
devices the bits of the CMPSL register will take precedence over the
associated Port F configuration and data output bits.
Interrupts
INTRODUCTION
Each device supports thirteen vectored interrupts. Interrupt
sources include Timer 0, Timer 1, Timer 2, Timer 3, Port L
Wakeup, Software Trap, MICROWIRE/PLUS, and External
Input.
All interrupts force a branch to location 00FF Hex in program
memory. The VIS instruction may be used to vector to the
appropriate service routine from location 00FF Hex.
The Software trap has the highest priority while the default
VIS has the lowest priority.
Each of the 13 maskable inputs has a fixed arbitration rank-
ing and vector.
Figure 16 shows the Interrupt Block Diagram.
DS012829-42
FIGURE 16. Interrupt Block Diagram
COP888xG/CS
Family
www.national.com
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