參數(shù)資料
型號： COPCSH984XXX/WM
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PDSO28
封裝： SOIC-28
文件頁數(shù)： 18/60頁
文件大?。?/td> 693K
代理商： COPCSH984XXX/WM
USART (Continued)
USART CONTROL AND STATUS REGISTERS
The operation of the USART is programmed through three
registers: ENU, ENUR and ENUI.
DESCRIPTION OF USART REGISTER BITS
ENU-USART Control and Status Register (Address at 0BA)
PEN
PSEL1
XBIT9/
CHL1
CHL0
ERR
RBFL
TBMT
PSEL0
Bit 7
Bit 0
PEN: This bit enables/disables Parity (7- and 8-bit modes
only). Read/Write, cleared on reset.
PEN = 0
Parity disabled.
PEN = 1
Parity enabled.
PSEL1, PSEL0: Parity select bits. Read/Write, cleared on
reset.
PSEL1 = 0, PSEL0 = 0
Odd Parity (if Parity enabled)
PSEL1 = 0, PSEL0 = 1
Even Parity (if Parity enabled)
PSEL1 = 1, PSEL0 = 0
Mark(1) (if Parity enabled)
PSEL1 = 1, PSEL0 = 1
Space(0) (if Parity enabled)
XBIT9/PSEL0: Programs the ninth bit for transmission when
the USART is operating with nine data bits per frame. For
seven or eight data bits per frame, this bit in conjunction with
PSEL1 selects parity. Read/Write, cleared on reset.
DS012829-14
FIGURE 12. USART Block Diagram
COP888xG/CS
Family
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