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| 型號(hào)： | COP8SEC520M |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-Bit CMOS ROM Based and OTP Microcontrollers with 4k Memory and 128 Bytes EERAM |
| 中文描述： | 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | PLASTIC, SOP-20 |
| 文件頁(yè)數(shù)： | 38/47頁(yè) |
| 文件大?。?/td> | 491K |
| 代理商： | COP8SEC520M |
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12.0 Instruction Set
(Continued)
12.4.9 No-Operation Instruction
The no-operation instruction does nothing, except to occupy
space in the program memory and time in execution.
No-Operation (NOP)
Note:
The VIS is a special case of the Indirect Transfer of Control addressing
mode, where the double byte vector associated with the interrupt is
transferred from adjacent addresses in the program memory into the
program counter (PC) in order to jump to the associated interrupt ser-
vice routine.
12.5 REGISTER AND SYMBOL DEFINITION
The following abbreviations represent the nomenclature
used
in
the
instruction
description
cross-assembler.
and
the
COP8
Registers
A
B
X
SP
PC
PU
PL
8-Bit Accumulator Register
8-Bit Address Register
8-Bit Address Register
8-Bit Stack Pointer Register
15-Bit Program Counter Register
Upper 7 Bits of PC
Lower 8 Bits of PC
Registers
C
HC
GIE
1 Bit of PSW Register for Carry
1 Bit of PSW Register for Half Carry
1 Bit of PSW Register for Global Interrupt
Enable
Interrupt Vector Upper Byte
Interrupt Vector Lower Byte
VU
VL
Symbols
[B]
[X]
MD
Mem
Meml
Memory Indirectly Addressed by B Register
Memory Indirectly Addressed by X Register
Direct Addressed Memory
Direct Addressed Memory or [B]
Direct Addressed Memory or [B] or
Immediate Data
8-Bit Immediate Data
Register Memory: Addresses F0 to FF
(Includes B, X and SP)
Bit Number (0 to 7)
Loaded with
Exchanged with
Imm
Reg
Bit
←
12.6 INSTRUCTION SET SUMMARY
ADD
ADC
A,Meml
A,Meml
ADD
ADD with Carry
A
←
A + Meml
A
←
A + Meml + C, C
←
Carry,
HC
←
Half Carry
A
←
A MemI + C, C
←
Carry,
HC
←
Half Carry
A
←
A and Meml
Skip next if (A and Imm) = 0
A
←
A or Meml
A
←
A xor Meml
Compare MD and Imm, Do next if MD = Imm
Compare A and Meml, Do next if A = Meml
Compare A and Meml, Do next if A
≠
Meml
Compare A and Meml, Do next if A
>
Meml
Do next if lower 4 bits of B
≠
Imm
Reg
←
Reg 1, Skip if Reg = 0
1 to bit, Mem (bit = 0 to 7 immediate)
0 to bit, Mem
If bit
#
, A or Mem is true do next instruction
Reset Software Interrupt Pending Flag
A
Mem
A
[X]
A
←
Meml
A
←
[X]
B
←
Imm
Mem
←
Imm
Reg
←
Imm
A
[B], (B
←
B
±
1)
A
[X], (X
←
X
±
1)
SUBC
A,Meml
Subtract with Carry
AND
ANDSZ
OR
XOR
IFEQ
IFEQ
IFNE
IFGT
IFBNE
DRSZ
SBIT
RBIT
IFBIT
RPND
X
X
LD
LD
LD
LD
LD
X
X
A,Meml
A,Imm
A,Meml
A,Meml
MD,Imm
A,Meml
A,Meml
A,Meml
#
Reg
#
,Mem
#
,Mem
#
,Mem
Logical AND
Logical AND Immed., Skip if Zero
Logical OR
Logical EXclusive OR
IF EQual
IF EQual
IF Not Equal
IF Greater Than
If B Not Equal
Decrement Reg., Skip if Zero
Set BIT
Reset BIT
IF BIT
Reset PeNDing Flag
EXchange A with Memory
EXchange A with Memory [X]
LoaD A with Memory
LoaD A with Memory [X]
LoaD B with Immed.
LoaD Memory Immed.
LoaD Register Memory Immed.
EXchange A with Memory [B]
EXchange A with Memory [X]
A,Mem
A,[X]
A,Meml
A,[X]
B,Imm
Mem,Imm
Reg,Imm
A, [B
±
]
A, [X
±
]
www.national.com
38
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