參數(shù)資料
型號(hào)： COP8SEC520M
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 微控制器/微處理器
英文描述： 8-Bit CMOS ROM Based and OTP Microcontrollers with 4k Memory and 128 Bytes EERAM
中文描述： 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PDSO20
封裝： PLASTIC, SOP-20
文件頁(yè)數(shù)： 15/47頁(yè)
文件大小： 491K
代理商： COP8SEC520M
5.0 Functional Description
(Continued)
5.10 CONTROL REGISTERS
CNTRL Register (Address X'00EE)
T1C3
Bit 7
The Timer1 (T1) and MICROWIRE/PLUS control register
contains the following bits:
T1C3
Timer T1 mode control bit
T1C2
Timer T1 mode control bit
T1C1
Timer T1 mode control bit
T1C0
Timer T1 Start/Stop control in timer
modes 1 and 2, T1 Underflow Interrupt
Pending Flag in timer mode 3
MSEL
Selects G5 and G4 as MICROWIRE/PLUS
signals SK and SO respectively
IEDG
External interrupt edge polarity select
(0 = Rising edge, 1 = Falling edge)
SL1 & SL0
Select the MICROWIRE/PLUS clock divide
by (00 = 2, 01 = 4, 1x = 8)
T1C2
T1C1
T1C0
MSEL
IEDG
SL1
SL0
Bit 0
PSW Register (Address X'00EF)
HC
Bit 7
The PSW register contains the following bits:
HC
Half Carry Flag
C
Carry Flag
T1PNDA Timer T1 Interrupt Pending Flag (Autoreload
RA in mode 1, T1 Underflow in Mode 2, T1A
capture edge in mode 3)
T1ENA
Timer T1 Interrupt Enable for Timer Underflow
or T1A Input capture edge
EXPND
External interrupt pending
BUSY
MICROWIRE/PLUS busy shifting flag
EXEN
Enable external interrupt
GIE
Global interrupt enable (enables interrupts)
The Half-Carry flag is also affected by all the instructions that
affect the Carry flag. The SC (Set Carry) and R/C (Reset
Carry) instructions will respectively set or clear both the carry
flags. In addition to the SC and R/C instructions, ADC,
SUBC, RRC and RLC instructions affect the Carry and Half
Carry flags.
C
T1PNDA
T1ENA
EXPND
BUSY
EXEN
GIE
Bit 0
ICNTRL Register (Address X'00E8)
Reserved
LPEN
T0PND
T0EN
μWPND
μWEN
T1PNDB
T1ENB
Bit 7
The ICNTRL register contains the following bits:
Reserved This bit is reserved and must be set to zero
LPEN
L Port Interrupt Enable (Multi-Input Wakeup/
Interrupt)
T0PND
Timer T0 Interrupt pending
T0EN
Timer T0 Interrupt Enable (Bit 12 toggle)
μWPND
MICROWIRE/PLUS interrupt pending
μWEN
Enable MICROWIRE/PLUS interrupt
T1PNDB
Timer T1 Interrupt Pending Flag for T1B cap-
ture edge
T1ENB
Timer T1 Interrupt Enable for T1B Input cap-
ture edge
Bit 0
6.0 Timers
Each device contains a very versatile set of timers (T0 and
T1). All timers and associated autoreload/capture registers
power up containing random data.
6.1 TIMER T0 (IDLE TIMER)
Each device supports applications that require maintaining
real time and low power with the IDLE mode. This IDLE
mode support is furnished by the IDLE timer T0, which is a
16-bit timer. The Timer T0 runs continuously at the fixed rate
of the instruction cycle clock, t
. The user cannot read or
write to the IDLE Timer T0, which is a count down timer.
The Timer T0 supports the following functions:
Exit out of the Idle Mode (See Idle Mode description)
WATCHDOG logic (See WATCHDOG description)
Start up delay out of the HALT mode
Figure 11is a functional block diagram showing the structure
of the IDLE Timer and its associated interrupt logic.
Bits 11 through 15 of the Idle Timer register can be selected
for triggering the IDLE Timer interrupt. Each time the se-
lected bit underflows (every 4k, 8k, 16k, 32k or 64k instruc-
tion cycles), the IDLE Timer interrupt pending bit T0PND is
set, thus generating an interrupt (if enabled), and bit 6 of the
Port G data register is reset, thus causing an exit from the
IDLE mode if the device is in that mode.
In order for an interrupt to be generated, the IDLE Timer in-
terrupt enable bit T0EN must be set, and the GIE (Global In-
terrupt Enable) bit must also be set. The T0PND flag and
T0EN bit are bits 5 and 4 of the ICNTRL register, respec-
tively. The interrupt can be used for any purpose. Typically, it
is used to perform a task upon exit from the IDLE mode. For
more information on the IDLE mode, refer to the Power Save
Modes section.
The Idle Timer period is selected by bits 0–2 of the ITMR
register Bits 3–7 of the ITMR Register are reserved and
must be “0”.
TABLE 3. Idle Timer Window Length
ITSEL2
ITSEL1
ITSEL0
Idle Timer Period
(Instruction Cycles)
4,096
8,192
16,384
32,768
65,536
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
The ITMR register is cleared on Reset and the Idle Timer pe-
riod is reset to 4,096 instruction cycles.
ITMR Register (Address X’0xCF)
Reserved (Must be
″
0
″
)
ITSEL2
ITSEL1
ITSEL0
Bit 7
Bit 3
Bit 0
Any time the IDLE Timer period is changed there is the pos-
sibility of generating a spurious IDLE Timer interrupt by set-
ting the T0PND bit. The user is advised to disable IDLE
Timer interrupts prior to changing the value of the ITSEL bits
of the ITMR Register and then clear the T0PND bit before at-
tempting to synchronize operation to the IDLE Timer.
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