參數(shù)資料
型號(hào)： COP8SEC520M
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 微控制器/微處理器
英文描述： 8-Bit CMOS ROM Based and OTP Microcontrollers with 4k Memory and 128 Bytes EERAM
中文描述： 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PDSO20
封裝： PLASTIC, SOP-20
文件頁(yè)數(shù)： 10/47頁(yè)
文件大?。?/td> 491K
代理商： COP8SEC520M
4.0 Pin Descriptions
The device I/O structure enables designers to reconfigure
the microcontroller’s I/O functions with a single instruction.
Each individual I/O pin can be independently configured as
output pin low, output high, input with high impedance or in-
put with weak pull-up device. A typical example is the use of
I/O pins as the keyboard matrix input lines. The input lines
can be programmed with internal weak pull-ups so that the
input lines read logic high when the keys are all open. With
a key closure, the corresponding input line will read a logic
zero since the weak pull-up can easily be overdriven. When
the key is released, the internal weak pull-up will pull the in-
put line back to logic high. This eliminates the need for exter-
nal pull-up resistors. The high current options are available
for driving LEDs, motors and speakers. This flexibility helps
to ensure a cleaner design, with fewer external components
and lower costs. Below is the general description of all avail-
able pins.
V
and GND are the power supply pins. All V
CC
and GND
pins must be connected.
CKI is the clock input. This can come from the Internal R/C
oscillator, or a crystal oscillator (in conjunction with CKO).
See Oscillator Description section.
RESET is the master reset input. See Reset description sec-
tion.
Each device contains two bidirectional 8-bit I/O ports (G and
L) and one bidirectional 4-I/O port (F), where each individual
bit may be independently configured as an input (Schmitt
trigger inputs on ports L and G), output or TRI-STATE under
program control. Three data memory address locations are
allocated for each of these I/O ports. Each I/O port has two
associated 8-bit memory mapped registers, the CONFIGU-
RATION register and the output DATA register. A memory
mapped address is also reserved for the input pins of each
I/O port. (See the memory map for the various addresses as-
sociated with the I/O ports.) Figure 5 shows the I/O port con-
figurations. The DATAand CONFIGURATION registers allow
for each port bit to be individually configured under software
control as shown below:
CONFIGURATION
Register
0
DATA
Register
0
Port Set-Up
Hi-Z Input
(TRI-STATE Output)
Input with Weak Pull-Up
Push-Pull Zero Output
Push-Pull One Output
0
1
1
1
0
1
Port L is an 8-bit I/O port. All L-pins have Schmitt triggers on
the inputs.
Port L supports the Multi-Input Wake Up feature on all eight
pins.
Port G is an 8-bit port. Pin G0, G2–G5 are bi-directional I/O
ports. Pin G6 is always a general purpose Hi-Z input. All pins
have Schmitt Triggers on their inputs.
Pin G1 serves as the
dedicated WATCHDOG output with weak pullup, if
WATCHDOG feature is selected by the mask option. The
pin is a general purpose I/O, if WATCHDOG feature is not
selected.
If WATCHDOG feature is selected, bit 1 of the Port
G configuration and data register does not have any effect
on Pin G1 setup. Pin G7 is either input or output depending
on the oscillator option selected. With the crystal oscillator
option selected, G7 serves as the dedicated output pin for
the CKO clock output. With the R/C oscillator option se-
lected, G7 serves as a general purpose Hi-Z input pin and is
also used to bring the device out of HALT mode with a low to
high transition on G7.
Since G6 is an input only pin and G7 is the dedicated CKO
clock output pin (crystal clock option) or general purpose in-
put (R/C or clock option), the associated bits in the data and
configuration registers for G6 and G7 are used for special
purpose functions as outlined below. Reading the G6 and G7
data bits will return zeroes.
Each device will be placed in the HALT mode by writing a “1”
to bit 7 of the Port G Data Register. Similarly the device will
be placed in the IDLE mode by writing a “1” to bit 6 of the
Port G Data Register.
Writing a “1” to bit 6 of the Port G Configuration Register en-
ables the MICROWIRE/PLUS to operate with the alternate
phase of the SK clock. The G7 configuration bit, if set high,
enables the clock start up delay after HALT when the R/C
clock configuration is used.
Config. Reg.
CLKDLY
Alternate SK
Data Reg.
HALT
IDLE
G7
G6
Port G has the following alternate features:
G7 CKO Oscillator dedicated output or general purpose in-
put
G6 SI (MICROWIRE Serial Data Input)
G5 SK (MICROWIRE Serial Clock)
G4 SO (MICROWIRE Serial Data Output)
G3 T1A (Timer T1 I/O)
G2 T1B (Timer T1 Capture Input)
G1 WDOUT WATCHDOG and/or CLock Monitor if WATCH-
DOG enabled, otherwise it is a general purpose I/O
(General purpose I/O is not available on COP8SER7)
G0 INTR (External Interrupt Input)
DS100973-10
FIGURE 5. I/O Port Configurations
www.national.com
10
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