參數(shù)資料
型號(hào)： COP8SEC520M
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 微控制器/微處理器
英文描述： 8-Bit CMOS ROM Based and OTP Microcontrollers with 4k Memory and 128 Bytes EERAM
中文描述： 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PDSO20
封裝： PLASTIC, SOP-20
文件頁(yè)數(shù)： 20/47頁(yè)
文件大?。?/td> 491K
代理商： COP8SEC520M
7.0 Power Saving Features
(Continued)
7.2 IDLE MODE
The device is placed in the IDLE mode by writing a
″
1
″
to the
IDLE flag (G6 data bit). In this mode, all activity, except the
associated on-board oscillator circuitry, the WATCHDOG
logic, the clock monitor and the IDLE Timer T0, is stopped.
The power supply requirements of the microcontroller in this
mode of operation are typically around 30% of normal power
requirement of the microcontroller.
As with the HALT mode, the device can be returned to nor-
mal operation with a reset, or with a Multi-Input Wakeup from
the L Port.
The microcontroller may also be awakened from the IDLE
mode after a selectable amount of time up to 65,536 instruc-
tion cycles, or 65.536 milliseconds with a 1 MHz instruction
clock frequency (10 MHz oscillator).
The IDLE timer period is selectable from one of five values,
4k, 8k, 16k, 32k or 64k instruction cycles. Selection of this
value is made through the ITMR register.
The user has the option of being interrupted with an under-
flow of the selected bit of the IDLE Timer T0. This condition
is latched into the T0PND pending flag. The interrupt can be
enabled or disabled via the T0EN control bit. Setting the
T0EN flag enables the interrupt and vice versa.
The user can enter the IDLE mode with the Timer T0 inter-
rupt enabled. In this case, when the T0PND bit gets set, the
device will first execute the Timer T0 interrupt service routine
and then return to the instruction following the
″
Enter Idle
Mode
″
instruction.
Alternatively, the user can enter the IDLE mode with the
IDLE Timer T0 interrupt disabled. In this case, the device will
resume normal operation with the instruction immediately
following the
″
Enter IDLE Mode
″
instruction.
The IDLE timer cannot be started or stopped under software
control, and it is not memory mapped, so it cannot be read or
written by the software. Its state upon Reset is unknown.
Therefore, if the device is put into the IDLE mode at an arbi-
trary time, it will stay in the IDLE mode for somewhere be-
tween 1 and the selected number of instruction cycles. Upon
reset the ITMR register is cleared and selects the 4,096 in-
struction cycle tap of the Idle Timer.
Note:
It is necessary to program two NOP instructions following both the set
HALT mode and set IDLE mode instructions. These NOP instructions
are necessary to allow clock resynchronization following the HALT or
IDLE modes.
For more information on the IDLE Timer and its associated
interrupt, see the description in the Timers Section.
DS100973-25
FIGURE 15. Wakeup from HALT
www.national.com
20
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