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參數(shù)資料
| 型號： | COP8SEC520M |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-Bit CMOS ROM Based and OTP Microcontrollers with 4k Memory and 128 Bytes EERAM |
| 中文描述： | 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | PLASTIC, SOP-20 |
| 文件頁數(shù)： | 22/47頁 |
| 文件大小： | 491K |
| 代理商： | COP8SEC520M |
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7.0 Power Saving Features
(Continued)
8.0 Interrupts
8.1 INTRODUCTION
Each device supports eight vectored interrupts. Interrupt
sources include Timer 0, Timer 1, EERAM Write Complete,
Port L Wakeup, Software Trap, MICROWIRE/PLUS, and Ex-
ternal Input.
All interrupts force a branch to location 00FF Hex in program
memory. The VIS instruction may be used to vector to the
appropriate service routine from location 00FF Hex.
The Software trap has the highest priority while the default
VIS has the lowest priority.
Each of the 7 maskable inputs has a fixed arbitration ranking
and vector.
Figure 18 shows the Interrupt Block Diagram.
DS100973-27
FIGURE 17. Multi-Input Wake Up Logic
DS100973-28
FIGURE 18. Interrupt Block Diagram
www.national.com
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