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| 型號(hào)： | COP8SBR9KMT8 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-Bit CMOS Flash Based Microcontroller with 32k Memory, Virtual EEPROM and Brownout |
| 中文描述： | 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PDSO56 |
| 封裝： | TSSOP-56 |
| 文件頁(yè)數(shù)： | 21/80頁(yè) |
| 文件大?。?/td> | 972K |
| 代理商： | COP8SBR9KMT8 |
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10.0 Functional Description
(Continued)
The format of the Option register is as follows:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
SECURITY
Reserved
WATCH
DOG
HALT
FLEX
Bits 7, 6 These bits are reserved and must be 0.
Bit 5
= 1
Security enabled. Flash Memory read and write
are not allowed except in User ISP/Virtual E
2
com-
mands. Mass Erase is allowed.
= 0
Security disabled. Flash Memory read and write
are allowed.
Bits 4, 3 These bits are reserved and must be 0.
Bit 2
= 1
WATCHDOG feature disabled. G1 is a general
purpose I/O.
= 0
WATCHDOG
feature
WATCHDOG output with weak pullup.
Bit 1
= 1
HALT mode disabled.
= 0
HALT mode enabled.
Bit 0
= 1
Execution following RESET will be from Flash
Memory.
= 0
Flash Memory is erased. Execution following RE-
SET will be from Boot ROM with the MICROWIRE/
PLUS ISP routines.
The COP8 assembler defines a special ROM section type,
CONF, into which the Option Register data may be coded.
The Option Register is programmed automatically by pro-
grammers that are certified by National.
The user needs to ensure that the FLEX bit will be set when
the device is programmed.
The following examples illustrate the declaration of the Op-
tion Register.
Syntax:
[label:].sect
config, conf
.db
value
enabled.
G1
pin
is
;1 byte,
;configures
;options
.endsect
Example: The following sets a value in the Option Register
and User Identification for a COP8SBR9VHA7. The Option
Register bit values shown select options: Security disabled,
WATCHDOG enabled HALT mode enabled and execution
will commence from Flash Memory.
.chip
8SBR
.sect
option, conf
.db
0x01
.endsect
...
.end
start
Note: All programmers certified for programming this family
of parts will support programming of the Option Register.
Please contact National or your device programmer supplier
for more information.
;wd, halt, flex
10.6 SECURITY
The device has a security feature which, when enabled,
prevents external reading of the Flash program memory. The
security bit in the Option Register determines, whether se-
curity is enabled or disabled. If the security feature is dis-
abled, the contents of the internal Flash Memory may be
read
by
external
programmers
MICROWIRE/PLUS serial interface ISP.
Security must be
enforced by the user when the contents of the Flash
Memory are accessed via the user ISP or Virtual EE-
PROM capability.
If the security feature is enabled, then any attempt to exter-
nally read the contents of the Flash Memory will result in the
value FF (hex) being read from all program locations (except
the Option Register). In addition, with the security feature
enabled, the write operation to the Flash program memory
and Option Register is inhibited. Page Erases are also inhib-
ited when the security feature is enabled. The Option Reg-
ister is readable regardless of the state of the security bit by
accessing location FFFF (hex). Mass Erase Operations are
possible regardless of the state of the security bit.
The security bit can be erased only by a Mass Erase of the
entire contents of the Flash unless Flash operation is under
the control of User ISP functions.
Note: The actual memory address of the Option Register is
7FFF (hex), however the MICROWIRE/PLUS ISP routines
require the address FFFF (hex) to be used to read the
Option Register when the Flash Memory is secured.
The entire Option Register must be programmed at one time
and cannot be rewritten without first erasing the entire last
page of Flash Memory.
or
by
the
built
in
10.7 RESET
The device is initialized when the RESET pin is pulled low or
the On-chip Brownout Reset is activated. The Brownout
Reset feature is not available on the COP8SDR9.
The following occurs upon initialization:
Port A: TRI-STATE (High Impedance Input)
Port B: TRI-STATE (High Impedance Input)
Port C: TRI-STATE (High Impedance Input)
Port D: HIGH
Port E: TRI-STATE (High Impedance Input)
Port F: TRI-STATE (High Impedance Input)
Port G: TRI-STATE (High Impedance Input)
Exceptions: If Watchdog is enabled, then G1 is Watch-
dog output. G0 and G2 have their weak pull-up en-
abled during RESET.
Port L: TRI-STATE (High Impedance Input)
PC: CLEARED to 0000
PSW, CNTRL and ICNTRL registers: CLEARED
SIOR:
UNAFFECTED after RESET with power already applied
10138911
FIGURE 8. Reset Logic
C
www.national.com
21
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| COP8SBR9LVA8 | 功能描述:8位微控制器 -MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| COP8SBR9LVA8/NOPB | 功能描述:8位微控制器 -MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| COP8SBR9LVA8NOPB | 制造商:National Semiconductor 功能描述:MCU 8-bit COP8 CISC 32KB Flash 3.3V/5V 68-Pin PLCC Rail |
| COP8SCE9 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| COP8SCE9HLQ7 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit CMOS Flash Microcontroller with 8k Memory, Virtual EEPROM and Brownout Reset |
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