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參數(shù)資料
| 型號： | CLC030 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | SMPTE 292M/259M Digital Video Serializer with Video and Ancilliary Data FIFOs and Integrated Cable Driver |
| 中文描述： | 的SMPTE 292M/259M數(shù)字視頻串行器，帶有視頻和輔助數(shù)據(jù)FIFO和內(nèi)置電纜驅(qū)動器 |
| 文件頁數(shù)： | 6/29頁 |
| 文件大?。?/td> | 329K |
| 代理商： | CLC030 |
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DC Electrical Characteristics
(Continued)
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 2, 3).
Symbol
Parameter
Conditions
I
DD
(2.5V)
2.5V Supply, Total
Colour Bar Pattern, Test
Circuit, Test Loads Shall
Apply
I
DD
(2.5V)
2.5V Supply, Total
Colour Bar Pattern, Test
Circuit, Test Loads Shall
Apply
Reference
V
DDD
, V
DDZ
,
V
DDPLL
Min
Typ
Max
Units
Power Supply Current,
V
CLK
= 27 MHz, NTSC
66
85
mA
Power Supply Current,
V
CLK
= 74.25 MHz, NTSC
V
DDD
, V
DDZ
,
V
DDPLL
85
110
mA
AC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 3).
Symbol
Parameter
f
VCLK
Parallel Video Clock
Frequency
DC
V
Video Clock Duty
Cycle
f
ACLK
Ancilliary Clock
Frequency
DC
A
Ancilliary Clock Duty
Cycle
t
r
, t
f
Input Clock and Data
Rise Time, Fall Time
BR
SDO
Serial Data Rate
(Notes 5, 6)
t
r
, t
f
Rise Time, Fall Time
20%–80%, (Note 6)
t
r
, t
f
Rise Time, Fall Time
20%–80%, (Note 5)
Output Overshoot
(Note 4)
t
j
Serial Output Jitter,
Intrinsic
t
j
Serial Output Jitter,
Intrinsic
t
LOCK
Lock Time
(Notes 5, 7) (SD Rates)
t
LOCK
Lock Time
(Notes 6, 7) (HD Rates)
t
S
Setup Time, Video
Data
t
H
Hold Time, Video
Data
t
S
Setup Time, Anc.
Data Port
t
H
Hold Time, Anc. Data
Port
Conditions
Reference
V
CLK
Min
Typ
Max
Units
27
74.25
MHz
V
CLK
45
50
55
%
A
CLK
V
CLK
MHz
A
CLK
45
50
55
%
10%–90%
V
CLK
, A
CLK
,
DV
N
, AD
N
SDO, SDO
SDO, SDO
SDO, SDO
SDO, SDO
SDO, SDO
1.0
1.5
3.0
ns
270
1,485
270
M
bps
ps
ps
%
500
5
270 M
bps
, (Notes 5, 9, 10)
200
ps
P-P
1,485 M
bps
, (Notes 6, 9, 10)
SDO, SDO
120
ps
P-P
15
15
ms
ms
Timing Diagram, (Note 4)
DV
N
to V
CLK
1.5
2.0
ns
Timing Diagram, (Note 4)
V
CLK
to DV
N
1.5
2.0
ns
Timing Diagram, (Note 4)
AD
N
to A
CLK
1.5
2.0
ns
Timing Diagram, (Note 4)
A
CLK
to AD
N
1.5
2.0
ns
Note 1:
“Absolute Maximum Ratings” are those parameter values beyond which the life and operation of the device cannot be guaranteed. The stating herein of
these maximums shall not be construed to imply that the device can or should be operated at or beyond these values. The table of “Electrical Characteristics”
specifies acceptable device operating conditions.
Note 2:
Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are referenced to V
SS
= 0V.
Note 3:
Typical values are stated for V
DDIO
= V
DDSD
= +3.3V, V
DDD
= V
DDPLL
= +2.5V and T
A
= +25C.
Note 4:
Spec. is guaranteed by design.
Note 5:
R
L
= 75
, AC-coupled
@
270 M
bps
, R
REF
LVL = R
REF
PRE = 4.75 k
1%, See
Test Loads
and
Test Circuit
.
Note 6:
R
L
= 75
, AC-coupled
@
1,485 M
bps
, R
REF
LVL = R
REF
PRE = 4.75 k
1%, See
Test Loads
and
Test Circuit
.
Note 7:
Measured from rising-edge of first DV
CLK
cycle until Lock Detect output goes high (true). Lock time includes format detection time plus PLL lock time.
Note 8:
Average value measured between rising edges computed over at least one video field.
Note 9:
Intrinsic timing jitter is measured in accordance with SMPTE RP 184-1996, SMPTE RP 192-1996 and the applicable serial data transmission standard,
SMPTE 259M-1997 or SMPTE 292M (proposed).Acolour bar test pattern is used. The value of f
SCLK
is 270 MHz or 360 MHz for SMPTE 259M, 540MHz for SMPTE
344M or 1,485 MHz for SMPTE 292M serial data rates. See
Timing Jitter Bandpass
section.
C
www.national.com
6
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