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參數(shù)資料
| 型號： | CLC030 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | SMPTE 292M/259M Digital Video Serializer with Video and Ancilliary Data FIFOs and Integrated Cable Driver |
| 中文描述： | 的SMPTE 292M/259M數(shù)字視頻串行器，帶有視頻和輔助數(shù)據(jù)FIFO和內(nèi)置電纜驅(qū)動器 |
| 文件頁數(shù)： | 19/29頁 |
| 文件大?。?/td> | 329K |
| 代理商： | CLC030 |
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Device Operation
(Continued)
Admission of ancilliary data packets into the FIFO is con-
trolled by the
ANC MASK[15:0]
and
ANC ID[15:0]
bits in the
control registers. The
ANC ID[15:0]
normally is set to a valid
16-bit code used for component ancilliary data packet iden-
tification as specified in SMPTE 291M-1998. The
ANC
MASK[15:0]
is a 16-bit word that can be used to selectively
control loading of packets with specific IDs (or ID ranges)
into the FIFO. When the
ANC MASK[15:0]
is set to FFFFh,
packets with any ID can be loaded into the FIFO. When any
bit or bits of the
ANC MASK[15:0]
are set to a logic-1, the
corresponding bit or bits of the
ANC ID[15:0]
are a don’t-
care when matching IDs of incoming packets. When the
ANC MASK[15:0]
is set to 0000h, the ANC ID of incoming
packets must match exactly, bit-for-bit the
ANC ID[15:0]
set
in the control register for the packets to be loaded into the
FIFO. The initial value of the
ANC MASK[15:0]
is FFFFh
and the
ANC ID[15:0]
is 0000h.
The
ANC PARITY MASK
bit when set disables parity check-
ing for the DATAID (DID) and SECONDARY DATAID (SDID)
in the ANC data packet. When reset, parity checking is
enabled, and, if a parity error occurs, the packet will not be
loaded.
The
FIFO INSERT ENABLE
bit in the control registers en-
ables insertion of ancilliary data stored in the FIFO into the
serial data stream. Data insertion is enabled when this bit is
set to a logic-1. This bit can be used to delay automatic
insertion of data into the serial data stream.
The CLC030 can keep track of up to 8 ancilliary packets in
the FIFO. Incoming packet length versus available space in
the FIFO is also tracked. The
MSG TRACK
bit in the control
registers, when set, enables tracking of packets in the FIFO.
MSG TRACK
also enables several other functions for con-
trol of packet traffic in the FIFO:
FIFO FLUSH DYN
,
FIFO
FLUSH STAT
,
MSG FLUSH DYN
, and
MSG FLUSH STAT
.
With message tracking enabled and
FIFO FLUSH DYN
set
to a logic-1, if a FIFO full condition is encountered, all
existing message packets in the FIFO will be flushed. The
current message packet will be left intact. When
FIFO
FLUSH DYN
is not set and a FIFO full condition is encoun-
tered, the FIFO will overrun and the
FIFO OVERRUN
flag
will be set.
FIFO FLUSH DYN
remains set until cleared.
Setting the
FIFO FLUSH STAT
bit to a logic-1 flushes the
FIFO. Data may not be loaded into the FIFO during
FIFO
FLUSH STAT
execution. Similarly,
FIFO FLUSH STAT
may
not be set when data is being input to the FIFO.
FIFO
FLUSH STAT
is automatically reset after this operation is
complete.
With message tracking enabled and
MSG FLUSH DYN
set
to a logic-1, the oldest message packet in the FIFO will be
flushed when the next message is written to the FIFO.
MSG
FLUSH DYN
remains set until cleared.
When
MSG FLUSH STAT
set to a logic-1, the oldest mes-
sage packet in the FIFO is flushed when data is not being
written to the FIFO.
MSG FLUSH STAT
is automatically
reset after this operation is complete.
The
FULL MSG REQ
(full message required) bit in the
control registers, when set, instructs the CLC030 to insert
only complete packets residing in the FIFO into the serial
data stream. When this bit is not set, messages of any
length, incomplete or partial, will be inserted into the serial
data stream. This function is not affected by
MSG TRACK
.
This function can be used to prevent overrunning available
space in the FIFO.
The
VANC
bit in the control registers, when set to a logic-1,
enables insertion of ancilliary data during the vertical blank-
ing interval (both active video and horizontal blanking por-
tions of the line).
SWITCH POINT REGISTERS 0 THROUGH 3 (Addresses
09h, 0Ah, 19h and 1Ah)
The
Line[10:0]
and
Protect[4:0]
bits define the vertical
switching point line and protected lines following the switch-
ing point line for fields 0 and 1 (or fields 1 and 2 as these are
sometimes referred to). The vertical switching point for com-
ponent digital standard definition formats is defined in
SMPTE RP 168-1993. The vertical switching point for
high-definition formats has the same basic definition. How-
ever, since the vertical switching point line is not necessarily
standardized among the various high-definition rasters,
these registers provide a convenient means whereby the
vertical switching point line and subsequent protected lines
may be specified by the user.
The
Line[10:0]
bits of registers
Switch Point 0 and 1
may
be loaded with a line number ranging from 0 to 1023 which
then specifies the switching point line for Field 0. The
Pro-
tect[4:0]
bits of register
Switch Point 1
determine the num-
ber of lines from 0 to 15 after the vertical switching point line
in which ancilliary data may not be inserted. LINE(0) is the
LSB and LINE(10) is the MSB for the
Line[10:0]
bits. Similar
ordering holds for the
Protect[4:0]
bits.
The
Line[10:0]
and
Protect[4:0]
bits of registers
Switch
Point 2 and 3
perform the same function as explained above
for the vertical switching point line for Field 1.
FORMAT REGISTERS 0 AND 1 (Addresses 0Bh and
0Ch)
The CLC030 may be set to process a single video format by
writing the appropriate data into the
FORMAT 0
register. The
Format Set[4:0]
bits confine the CLC030 to recognize and
process only one of the fourteen specified types of standard
or high definition formats. The
Format Set[4:0]
bits may not
be used to confine device operation to a range of standards.
The available formats and codes are detailed in Table 4
Generally speaking, the
Format Set[4:0]
codes indicate or
group the formats as follows:
Format Set[4]
is set for the HD
formats and reset for the SD formats.
Format Set[3]
when
set indicates that PAL data is being processed. When reset
NTSC data is being processed.
Format Set[2:0]
correspond
to one of the sub-standards given in the table. Note that the
CLC030 makes no distinction in formats resulting from the
processing of data at 74.25MHz or 74.176MHz.
The CLC030 can automatically determine the format of the
incoming parallel data. The result of this operation is stored
in the
FORMAT 1
register. The
Format[4:0]
bits identify
which of the many possible video data standards that the
CLC030 can process is being received. These format codes
follow the same arrangement as for the
Format Set[4:0]
bits. These formats and codes are given in Table 4 Bit
Format[4]
when set indicates that HD data is being pro-
cessed. When reset, SD data is indicated.
Format[3]
when
set indicates that PAL data is being processed. When reset
NTSC data is being processed.
Format[2:0]
correspond
with one of the sub-standards given in the table.
C
www.national.com
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