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參數(shù)資料
| 型號： | CLC030 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | SMPTE 292M/259M Digital Video Serializer with Video and Ancilliary Data FIFOs and Integrated Cable Driver |
| 中文描述： | 的SMPTE 292M/259M數(shù)字視頻串行器，帶有視頻和輔助數(shù)據(jù)FIFO和內置電纜驅動器 |
| 文件頁數(shù)： | 28/29頁 |
| 文件大小： | 329K |
| 代理商： | CLC030 |
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Application Information
Complete details for the SD130ASM evaluation PCB are
available on National’s WEB site. This circuit demonstrates
the capabilities of the CLC030 and allows its evaluation in a
native configuration. An assembled demonstration board kit,
part number SD130EVK, complete with operating instruc-
tions, drawing package and list of materials is available.
Contact the Interface Products Group or the Serial Digital
Video and Interface Applications Group for ordering informa-
tion. Complete circuit board layouts, schematics and other
information for the SD130EVK are also available on Nation-
al’s WEB site in the application information for this device.
For latest product details and availability information, please
see: www.national.com/appinfo/interface.
PCB Layout and Power System Bypass
Recommendations
Circuit board layout and stack-up for the CLC030 should be
designed to provide noise-free power to the device. Good
layout practice also will separate high frequency or high level
inputs and outputs to minimize unwanted stray noise pickup,
feedback and interference. Power system performance may
be greatly improved by using thin dielectrics (4 to 10 mils) for
power/ground sandwiches. This increases the intrinsic ca-
pacitance of the PCB power system which improves power
supply filtering, especially at high frequencies, and makes
the value and placement of external bypass capacitors less
critical. External bypass capacitors should include both RF
ceramic and tantalum electrolytic types. RF capacitors may
use values in the range 0.01 μF to 0.1 μF. Tantalum capaci-
tors may be in the range 2.2 μF to 10 μF. Voltage rating for
tantalum capacitors should be at least 5X the power supply
voltage being used. It is recommended practice to use two
vias at each power pin of the CLC030 as well as all RF
bypass capacitor terminals. Dual vias reduce the intercon-
nect inductance by up to half, thereby reducing interconnect
inductance and extending the effective frequency range of
the bypass components.
The outer layers of the PCB may be flooded with additional
V
(ground) plane. These planes will improve shielding and
isolation as well as increase the intrinsic capacitance of the
power supply plane system. Naturally, to be effective, these
planes must be tied to the V
power supply plane at fre-
quent intervals with vias. Frequent via placement also im-
proves signal integrity on signal transmission lines by pro-
viding short paths for image currents which reduces signal
distortion. The planes should be pulled back from all trans-
mission lines and component mounting pads a distance
equal to the width of the widest transmission line or the
thickness of the dielectric separating the transmission line
from the internal power or ground plane(s) whichever is
greater. Doing so minimizes effects on transmission line
impedances and reduces unwanted parasitic capacitances
at component mounting pads.
The CLC030 uses two power supply voltages, 2.5 and 3.3
volts. These supplies connect to the device through seven
sets of independent power input pins. The function and
system supplied through these is given in the Pin Description
Table. The power supply voltages normally share a common
0 volt or ground return system. Either a split plane or sepa-
rate power planes can be used to supply the positive volt-
ages to the device.
In especially noisy power supply environments, such as is
often the case when using switching power supplies, sepa-
rate filtering may be used at the CLC030’s PLL analog, PLL
digital and serial output driver power pins. The CLC030 was
designed for this situation. The digital section, PLL and
output driver power supply feeds are independent. See the
Pin Description Table and the Connection Diagram for de-
tails. Supply filtering may take the form of L-section or pi-
section, L-C filters in series with these V
inputs. Such
filters are available in a single package from several manu-
facturers. Despite being independent feeds, all device power
supplies should be applied simultaneously as from a com-
mon source.
Processing Non-Supported Raster Formats
The number and type of HD raster formats has proliferated
greatly since the CLC030 was designed. Though not specifi-
cally capable of fully or automatically processing these new
formats, the CLC030 may still be capable of serializing them.
The user is encouraged to experiment with processing of
these formats keeping in mind that the CLC030 has not been
tested to handle raster formats other than those detailed in
Table 4 Therefore, the results from attempts to process
non-supported formats is not guaranteed. The following
guidelines concerning device setup are provided to aid the
user in configuring the CLC030 to attempt limited processing
of these other raster formats. In general, the device is con-
figured to defeat its format and TRS detection function and to
limit operation to a general HD format type. (The user should
consult Table 4 for guidance on the format groups similar to
the non-supported one to be processed). Since most
non-supported formats are in the HD realm, the CLC030
should be configured to operate in HD-ONLY mode by set-
ting bit-5 of the FORMAT 0 register (address 0Bh). Also, the
device should be further configured by loading the FORMAT
SET[4:0] bits of this register with the general HD sub-format
code. The complete data word for this general HD
sub-format code with HD-ONLY bit set is 330h. Since this
format differs from those in the table, the EAV/SAV indicators
are disabled. Without these indicators, line numbering and
CRC insertion are disabled and ancilliary data insertion will
not function. Pre-processing of the parallel data ahead of the
CLC030 will be required to insert CRC data and line num-
bering.
C
www.national.com
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| CLC031AVEC | SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video and Ancillary Data FIFOs |
| CLC031 | SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video and Ancilliary Data FIFOs |
| CLC031VEC | SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video and Ancilliary Data FIFOs |
| CLC034 | SMPTE 292M / 259M Adaptive Cable Equalizer |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CLC030_06 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:SMPTE 292M/259M Digital Video Serializer with Video and Ancillary Data FIFOs and Integrated Cable Driver |
| CLC030AVEC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CLC030VEC | 功能描述:IC SERIALIZER VIDEO DGTL 64-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 串行器，解串行器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 功能:解串器 數(shù)據(jù)速率:2.5Gbps 輸入類型:串行 輸出類型:并聯(lián) 輸入數(shù):- 輸出數(shù):24 電源電壓:1.8 V ~ 3.3 V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:64-TQFP 裸露焊盤 供應商設備封裝:64-TQFP-EP（10x10） 包裝:管件 |
| CLC031 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video and Ancilliary Data FIFOs |
| CLC03-10N_-RC | 制造商:ALLIED 制造商全稱:Allied Components International 功能描述:Ceramic Core Laser Cut Chip Inductor |
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