參數(shù)資料
型號(hào)： CLC030
廠商： National Semiconductor Corporation
英文描述： SMPTE 292M/259M Digital Video Serializer with Video and Ancilliary Data FIFOs and Integrated Cable Driver
中文描述： 的SMPTE 292M/259M數(shù)字視頻串行器，帶有視頻和輔助數(shù)據(jù)FIFO和內(nèi)置電纜驅(qū)動(dòng)器
文件頁(yè)數(shù)： 10/29頁(yè)
文件大?。?/td> 329K
代理商： CLC030
Device Operation
(Continued)
pendent of the video data clock,
VCLK
. Inputs
AD[9:0]
,
RD/WR
and
ANC/CTRL
have internal pull down devices.
ACLK
does not have an internal pull down device.
Control Data Read Functions
Control data
is input to and output from the CLC030 using
the lower-order 8 bits
AD[7:0]
of the Ancilliary/Control Data
Port. This control data initializes, monitors and controls op-
eration of the CLC030. The upper two bits
AD[9:8]
of the
port function as handshaking signals with the device access-
ing the port.
AD[9:8]
must be driven as 00b (0XXh, where
XX are AD[7:0]) when either a control register read or write
address is being written to the port.
AD[9:8]
must be driven
as 11b (3XXh, where XX are AD[7:0]) when control data is
being written to the port. When control data is being read
from the port, the CLC030 will output
AD[9:8]
as 10b (2XXh,
where XX are output data AD[7:0]) and may be ignored by
the monitoring system.
Note:
When power is first applied to the device or after it is
reset, the
Ancilliary and Control Data Port
must be initial-
ized to receive data. This is done by toggling
ACLK
three (3)
times.
Figure 1shows the sequence of clock and control signals for
reading control data from the ancilliary/control data port.
Control data read mode
is invoked by making the
ANC/CTRL
input low and the
RD/WR
input high. The 8-bit
address of the control register set to be accessed is input to
the port on bits
AD[7:0]
. The address is captured on the
rising edge of
ACLK
. When a control register read address
is being written to the port,
AD[9:8]
must be driven as 00b
(0XXh, where XX are AD[7:0]). When control data is being
read from the port, the CLC030 will output
AD[9:8]
as 10b
(2XXh, where XX are output data AD[7:0]) and may be
ignored by the monitoring system. Data being output from
the selected register is driven by the port immediately follow-
ing the rising edge of
ACLK
or when the address signals are
removed. For optimum system timing, the address signals
driving the port should be removed immediately after the
address is clocked into the device and before or coincident
with the falling edge of
ACLK
at the end of the address
cycle. Output data remains stable until the next rising edge
of
ACLK
and may be read by external devices at any time
after the removal of the address signal. This second clock
resets the port from drive to receive mode and readies the
port for another access cycle.
Example:
Read the Full-field Flags via the AD port.
1.
Set
ANC/CTRL
to a logic-low.
2.
Set
RD/WR
to a logic-high.
3.
Present 001h to
AD[9:0]
as the register address.
4.
Toggle
ACLK
.
5.
Release the bus driving the AD port.
6.
Read the data present on the AD port. The Full-field
Flags are bits AD[4:0].
7.
Toggle
ACLK
to release the AD port.
Control Data Write Functions
Figure 2shows the sequence of clock and control signals for
writing control data to the ancilliary/control data port. The
control data write mode
is similar to the read mode. Con-
trol data write mode is invoked by making the
ANC/CTRL
input low and the
RD/WR
input low. The 8-bit address of the
control register set to be accessed is input to the port on bits
AD[7:0]
. The address is captured on the rising edge of
ACLK
. The address data is removed after being clocked into
the device or before the falling edge of
ACLK
. Next, the
control data is presented to the port bits
AD[7:0]
and written
into the selected register on the next rising edge of
ACLK
.
When a control register write address is being written to the
port,
AD[9:8]
must be driven as 00b (0XXh, where XX are
AD[7:0]). When control data is being written to the port,
AD[9:8]
must be driven as 11b (3XXh, where XX are
AD[7:0]). Control data written into the registers may be read
out non-destructively in most cases.
Example:
Setup (without enabling) the TPG Mode via the
AD port using the 1125 line, 30 frame, 74.25MHz, interlaced
component (SMPTE 274M) colour bars as test pattern. The
TPG may be enabled after setup using the Multi-function I/O
port or by the control registers.
1.
Set
ANC/CTRL
to a logic-low.
2.
Set
RD/WR
to a logic-low.
3.
Present 00Dh to
AD[9:0]
as the Test 0 register address.
4.
Toggle
ACLK
.
5.
Present 027h to
AD[9:0]
as the register data.
6.
Toggle
ACLK
.
C
www.national.com
10
相關(guān)PDF資料
PDF描述
CLC031A SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video and Ancillary Data FIFOs
CLC031AVEC SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video and Ancillary Data FIFOs
CLC031 SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video and Ancilliary Data FIFOs
CLC031VEC SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video and Ancilliary Data FIFOs
CLC034 SMPTE 292M / 259M Adaptive Cable Equalizer
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CLC030_06 制造商:NSC 制造商全稱:National Semiconductor 功能描述:SMPTE 292M/259M Digital Video Serializer with Video and Ancillary Data FIFOs and Integrated Cable Driver
CLC030AVEC 制造商:Rochester Electronics LLC 功能描述:- Bulk
CLC030VEC 功能描述:IC SERIALIZER VIDEO DGTL 64-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 串行器，解串行器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 功能:解串器 數(shù)據(jù)速率:2.5Gbps 輸入類型:串行 輸出類型:并聯(lián) 輸入數(shù):- 輸出數(shù):24 電源電壓:1.8 V ~ 3.3 V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:64-TQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-TQFP-EP（10x10） 包裝:管件
CLC031 制造商:NSC 制造商全稱:National Semiconductor 功能描述:SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video and Ancilliary Data FIFOs
CLC03-10N_-RC 制造商:ALLIED 制造商全稱:Allied Components International 功能描述:Ceramic Core Laser Cut Chip Inductor
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*