參數(shù)資料
型號(hào)： CLC030
廠商： National Semiconductor Corporation
英文描述： SMPTE 292M/259M Digital Video Serializer with Video and Ancilliary Data FIFOs and Integrated Cable Driver
中文描述： 的SMPTE 292M/259M數(shù)字視頻串行器，帶有視頻和輔助數(shù)據(jù)FIFO和內(nèi)置電纜驅(qū)動(dòng)器
文件頁(yè)數(shù)： 14/29頁(yè)
文件大小： 329K
代理商： CLC030
Device Operation
(Continued)
an internal pull down device, is mandatory to prevent admis-
sion of noise or unwanted signals at any time, especially
during power-up or reset sequences. It is strongly recom-
mended that VCLK not be applied until device initialization
and configuration is completed.
Example:
Enable the TPG Mode to use the NTSC 270Mbps
colour bars as the BIST and TPG pattern. Enable TPG
operation using the I/O port.
1.
Set
ANC/CTRL
to a logic-low.
2.
Set
RD/WR
to a logic-low.
3.
Present 00Dh to
AD[9:0]
as the
TEST 0
register ad-
dress.
4.
Toggle
ACLK
.
5.
Present 303h to
AD[9:0]
as the register data (525 line,
30 frame, 27MHz, NTSC 4x3, colour bars (SMPTE
125M)).
6.
Toggle
ACLK
.
7.
Set
TPG ENABLE
(I/O Port, bit 7) to a logic-high.
8.
Toggle
ACLK
.
9.
The
PASS/FAIL
indicator (I/O Port, bit 6) is monitored
for the result of the test. Alternatively, the
TEST 0
regis-
ter may be read. Bit 7 is the Pass/Fail indicator bit.
CONFIGURATION AND CONTROL REGISTERS
The configuration and control registers store data which
configures the operational modes of the CLC030 or which
result from its operation. Many of these registers may be
mapped to the multi-function I/O bus to make them available
as external I/O functions. These functions and initial values
are summarized in Table 1 and detailed in Table 2 The
power-on default condition for the multi-function I/O port is
indicated in Table 1 and detailed in Table 6
C
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14
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