參數(shù)資料
型號(hào)： CLC030
廠商： National Semiconductor Corporation
英文描述： SMPTE 292M/259M Digital Video Serializer with Video and Ancilliary Data FIFOs and Integrated Cable Driver
中文描述： 的SMPTE 292M/259M數(shù)字視頻串行器，帶有視頻和輔助數(shù)據(jù)FIFO和內(nèi)置電纜驅(qū)動(dòng)器
文件頁(yè)數(shù)： 12/29頁(yè)
文件大?。?/td> 329K
代理商： CLC030
Device Operation
(Continued)
MULTI-FUNCTION I/O PORT
The
multi-function I/O port
can be configured to provide
immediate access to many control and indicator functions
within the CLC030 configuration and control registers. The
individual pins comprising this port are assigned as input or
output for selected bits in the control data registers. The
multi-function I/O port is configured by way of an 8x6-bit
register bank, configuration and control registers
I/O pin 0
CONFIG
through
I/O pin 7 CONFIG
. The contents of these
registers determine whether the port bits function as inputs
or outputs and to which register element each port bit is
assigned. Port bits may be assigned to access different
register elements or any or all port bits may be assigned to
access the same register element (an unlikely or unusual
situation). Controls and indicators that are accessible by the
port and their corresponding selection addresses are given
in the I/O Pin Configuration Register Addresses, Table 6
Table 2 gives the control register bit assignments.
Caution:
When writing data into the control registers via the
multi-function I/O port,
ACLK
must be toggled to register the
data as shown in Figure 4 It is not necessary to toggle
ACLK
when reading data from the multi-function I/O port.
Example:
Program multi-function I/O port bit-0 as the CRC
Luma Error bit output.
1.
Set
ANC/CTRL
to a logic-low.
2.
Set
RD/WR
to a logic-low.
3.
Present 00Fh to
AD[9:0]
as the
I/O PIN 0 CONFIG
register address.
4.
Toggle
ACLK
.
5.
Present 310h to
AD[9:0]
as the register data.
6.
Toggle
ACLK
.
EDH/CRC SYSTEM
The CLC030 has
EDH
and
CRC character generation and
insertion
circuitry. The EDH system functions as described
in SMPTE Recommended Practice RP-165. The CRC sys-
tem functions as specified in SMPTE 292M. The
EDH/CRC
polynomial generators
accept parallel data from the input
register and generate the EDH and CRC check words for
insertion in the serial data. Incoming parallel data is checked
for errors and the EDH flags are updated automatically. EDH
check words and status flags for SDTV data are generated
using the polynomial X
16
+ X
12
+ X
6
+ 1 per SMPTE RP165.
EDH check words are inserted in the serial data stream at
the correct positions in the ancilliary data space and format-
ted per SMPTE 291M. Generation and automatic insertion of
the EDH check words is controlled by
EDH Force
and
EDH
Enable
bits in the control registers. After a reset, the initial
state of all EDH and CRC check characters is 00h.
The SMPTE 292M high definition video standard employs
CRC
(cyclic redundancy check codes) error checking in-
stead of EDH. The CRC consists of two 18-bit words gener-
ated using the polynomial X
18
+ X
5
+ X
4
+ 1 per SMPTE
292M. One CRC is used for luminance and one for chromi-
nance data. CRC data is inserted at the required place in the
video data according to SMPTE 292M. The CRCs appear in
the data stream following the EAV and line number charac-
ters.
EDH and CRC errors are reported in the EDH0, EDH1, and
EDH2 register sets of the configuration and control registers.
PHASE-LOCKED LOOP SYSTEM
The
phase-locked loop
(PLL) system generates the output
serial data clock at 10x (standard definition) or 20x (high
definition) the parallel data clock frequency. This system
consists of a VCO, divider chain, phase-frequency detector
and internal loop filter. The VCO free-running frequency is
internally set. The PLL automatically generates the appropri-
ate frequency for the serial clock rate using the parallel data
clock (VCLK) frequency as its reference. Loop filtering is
internal to the CLC030. The VCO has separate analog and
digital power supply feeds: V
pin 62, V
pin 61,
V
pin 1, and V
pin 2. These may be separately
supplied power via external low-pass filters, if desired. PLL
acquisition time is less than 200μs
@
1,485 Mbps. The VCO
halts when VCLK signal is not present or is inactive.
A
LOCK DETECT
indicator function is available as a bit in
the
VIDEO INFO 0
control registers.
LOCK DETECT
is a
logic-1 when the PLL is locked and can be assigned as an
output on the multifunction I/O port. The power-on or reset
default assigns
LOCK DETECT
as I/O Port bit 4. This func-
tion also includes logic to check the stability of the device
after the digital logic reset is released following PLL lock. If
the system is not fully stable, the logic is automatically reset.
LOCK DETECT
also combines the function of indicating that
DS200003-11
FIGURE 3. Ancilliary Data Write Timing
DS200003-12
FIGURE 4. I/O Port Data Write Timing
C
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12
相關(guān)PDF資料
PDF描述
CLC031A SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video and Ancillary Data FIFOs
CLC031AVEC SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video and Ancillary Data FIFOs
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CLC030_06 制造商:NSC 制造商全稱:National Semiconductor 功能描述:SMPTE 292M/259M Digital Video Serializer with Video and Ancillary Data FIFOs and Integrated Cable Driver
CLC030AVEC 制造商:Rochester Electronics LLC 功能描述:- Bulk
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CLC031 制造商:NSC 制造商全稱:National Semiconductor 功能描述:SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video and Ancilliary Data FIFOs
CLC03-10N_-RC 制造商:ALLIED 制造商全稱:Allied Components International 功能描述:Ceramic Core Laser Cut Chip Inductor
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