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參數(shù)資料
| 型號(hào)： | CLC016 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Data Retiming PLL with Automatic Rate Selection(帶自動(dòng)速率選擇的數(shù)據(jù)重定時(shí)PLL) |
| 中文描述： | 數(shù)據(jù)定時(shí)鎖相環(huán)（帶自動(dòng)速率選擇的數(shù)據(jù)重定時(shí)鎖相環(huán)），具有自動(dòng)速率選擇 |
| 文件頁(yè)數(shù)： | 8/20頁(yè) |
| 文件大小： | 435K |
| 代理商： | CLC016 |
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Product Description
(Continued)
Pin Definitions
Name
DDI, DDI
Pin #
5, 6
Description
Differential (ECL, PECL) data
inputs.
Differential collector (ECL,
PECL compatible) clock outputs
Differential collector (ECL,
PECL compatible) retimed data
outputs
Bi-directional (TTL, CMOS)
VCO data rate bus. See Table 3
for state table.
VCO rate configuration resistors
(n = 0, 1, 2, 3).
Return for R
n
Loop unlock output (TTL,
CMOS) indicator. High when
loop is unlocked or
harmonic-locked.
Carrier detector (TTL, CMOS)
output. Low when no signal is
present.
Output mute (TTL, CMOS)
control. Connect to CD to latch
outputs when no signal is
present.
Auto- or manual-rate mode
control (TTL, CMOS) input.
Assert high for auto-rate mode.
ARS oscillator enable and rate
latch enable (TTL, CMOS)
input. Connect to SER (see
diagrams) for auto-rate mode.
External capacitor connections
for controlling the rate of the
ARS search.
VCO control lines. Loop filter
connects across these and FD.
Frequency detector output. C
Z
must connect from FD to V
C
.
Positive supply pins (ground or
+5V).
Negative supply pins (5.2V or
ground).
SCO,
SCO
SDO,
SDO
23, 22
25, 24
RDO,
RD1
20, 21
R
n
13, 14,
15, 17
18
4
RTN
SER
CD
19
MUTE
28
AUTO
16
ACQ/WR
8
C
ARS
2
V
C
, V
C
12, 9
FD
10
V
CC
7, 26
V
EE
1, 3, 11,
27
Operation Description
The CLC016 Data Retiming PLL, Figure 3 has three main
functions: Frequency Detector (FD), Phase-Locked Loop
(PLL) and Auto-Rate Select (ARS).
The Frequency Detector detects the frequency difference
between the input data rate and the VCO frequency, and
forces a rapid change in VCO frequency to minimize that dif-
ference. As the frequency difference approaches zero, the
PLL acquires phase lock and the Frequency Detector be-
comes inactive. In Auto-Rate Select mode, the Frequency
Detector requests the ARS function to search for a new data
rate.
The PLL consists of a Voltage Controlled Oscillator (VCO), a
Phase Detector (PD), and an external Loop Filter (LF). The
PLL recovers a low-jitter clock for data retiming. The data is
re-synchronized (retimed) at the Data Latch. The data and
clock are buffered outputs.
TheARS block has two modes of operation:Auto-Rate Mode
(ARM) and Manual-Rate Mode (MRM). Once the ARS func-
tion is activated (ARM), it sequences through the user-
selected data rates until phase lock is achieved. The user
has control over the rate at which ARS steps through the
data rates (see
Auto-Rate Selection
section).
The Carrier Detect (CD) block detects the presence of input
data and is an input to the ARS block. When CD is con-
nected to MUTE and no data is present, the clock and data
outputs are latched.
DS100087-15
FIGURE 3. Functional Block Diagram
C
www.national.com
8
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| CLC016_02 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Data Retiming PLL with Automatic Rate Selection |
| CLC016ACQ | 制造商:Texas Instruments 功能描述:Data Retiming PLL w/Auto Rate,CLC016ACQ |
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| CLC016AJQ | 制造商:Texas Instruments 功能描述:Data Retiming PLL w/Auto Rate,CLC016AJQ |
| CLC016AJQ | 制造商:Texas Instruments 功能描述:IC DATA RETIMING PLL SMD PLCC28 |
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