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參數(shù)資料
| 型號： | CLC016 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Data Retiming PLL with Automatic Rate Selection(帶自動速率選擇的數(shù)據(jù)重定時(shí)PLL) |
| 中文描述： | 數(shù)據(jù)定時(shí)鎖相環(huán)（帶自動速率選擇的數(shù)據(jù)重定時(shí)鎖相環(huán)），具有自動速率選擇 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 435K |
| 代理商： | CLC016 |
Electrical Characteristics
(Continued)
(V
CC
= 0V, V
EE
= 5V, R
BW
= 500
; C
Z
= 0.1 μF; C
P
= 82 pF; R
n
= 3504, C
ARS
= 0.1 μF; unless specified).
Parameter
Conditions
Typ
+25C
Min/Max
+25C
Min/Max
Full Temp.
Range
Units
STATIC PERFORMANCE
CD, UNL, RDO/RD1
Current Output — LOW, I
OL
Current Output — HIGH, I
OH
TIMING PERFORMANCE
Delay: SCO to SDO, t
d
SCO Duty Cycle
Rise/Fall Time: SCO, SDO, t
r
/t
f
(Note 9)
V
OL
≤
V
EE
+0.5V
V
OH
≥
V
CC
0.5V
800
700
μA
μA
200
50
230
ps
%
ps
(Note 3)
20%–80%, R
collector
= 75
(Note 10)
44/56
44/56
SDO Duty Cycle Distortion
Minimum Setup Time:
RDO/RD1 to ACQ/WR, t
SU
Minimum Hold Time:
ACQ/WR to SS1/SS0, t
h
Minimum Pulse Width:
ACQ/WR, t
w
ARS Oscillator Period, t
OSC
CD Pulse Width, t
PW
MUTE Response Time, t
M
35
4
ps
ns
20
20
3
20
20
ns
5
20
20
ns
(Note 3)
(Note 11)
10.5
1
5
8.5/15.5
ms
μs
ns
Note 1:
“Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2:
Min/Max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined
from tested parameters.
Note 3:
J-level spec. is 100% tested at +25C.
Note 4:
Peak-to-peak jitter is defined as 6 times the rms jitter.
Note 5:
Tracking and capture range are specified as a percentage of the input data rate f
CLK
. The minimum and maximum are guaranteed so long as R
n
has been
chosen according to the equation in
Resistor Selection for Data Rates.
Note 6:
Average data transition density of 1 transition per 2 bit cells.
Note 7:
When the value of R
BW
changes it is necessary to also change the values of C
P
and C
Z
. See
Loop Filter Design.
Note 8:
This information is provided for system troubleshooting purposes only.
Note 9:
RD0/RD1 are inputs when AUTO = 0 and outputs when AUTO = 1.
Note 10:
Includes typical pc board capacitance.
Note 11:
The CD circuit is a retriggerable one-shot which retriggers on every data transition.
Note 12:
Human body model, 1.5 k
in series with 100 pF.
Note 13:
To maintain specified performance, SCO/ SCO and SDO/SDO should not drop below this level.
C
www.national.com
4
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| CLC016_02 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Data Retiming PLL with Automatic Rate Selection |
| CLC016ACQ | 制造商:Texas Instruments 功能描述:Data Retiming PLL w/Auto Rate,CLC016ACQ |
| CLC016ACQ/NOPB | 功能描述:IC DATA RETIMING PLL 28-PLCC RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| CLC016AJQ | 制造商:Texas Instruments 功能描述:Data Retiming PLL w/Auto Rate,CLC016AJQ |
| CLC016AJQ | 制造商:Texas Instruments 功能描述:IC DATA RETIMING PLL SMD PLCC28 |
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