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參數(shù)資料
| 型號(hào)： | CLC016 |
| 廠(chǎng)商： | National Semiconductor Corporation |
| 英文描述： | Data Retiming PLL with Automatic Rate Selection(帶自動(dòng)速率選擇的數(shù)據(jù)重定時(shí)PLL) |
| 中文描述： | 數(shù)據(jù)定時(shí)鎖相環(huán)（帶自動(dòng)速率選擇的數(shù)據(jù)重定時(shí)鎖相環(huán)），具有自動(dòng)速率選擇 |
| 文件頁(yè)數(shù)： | 11/20頁(yè) |
| 文件大小： | 435K |
| 代理商： | CLC016 |
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Product Description
(Continued)
As an example, assume that the amount of jitter peaking that
can be tolerated is 0.05 dB. From the jitter peaking design
equation (or from Figure 6) the required value of
α
is:
α
.
0.05[0.134 + (0.058)(0.05)] = 0.007
Now assuming that the loop bandwidth is 644 kHz and that
the value of R
BW
is 500
, the value of C
Z
is:
The value of C
also affects the acquisition performance of
the PLL. Estimate the acquisition time with the following
equation:
where t
ACQ
x f
CLK
is the acquisition time in number of bit
cells.
Selecting C
P
Capacitor C
establishes a high frequency pole in the loop
filter to remove high frequency spectral components from the
phase detector. The pole frequency f
P
is:
In general, the pole should be set at least a factor of 4 above
the PLL bandwidth, f
BW
. Therefore, select C
P
using:
For example, if R
is 500
and f
BW
is 644 kHz, then an ap-
propriate value for C
P
is:
Choosing a value for C
larger than the value recommended
by the selection equation will introduce jitter peaking. Reduc-
ing the value of C
P
below that recommended by the selec-
tion equation is acceptable, but will result in some increase
in jitter. This is most noticeable with large fractional loop
bandwidths.
In addition, C
can affect the ability of the PLL to acquire
lock, especially at high data rates. Because of this, it is rec-
ommended to eliminate C
P
entirely for the condition of high
data rate (
>
300 Mbps) combined with narrow loop band-
width (
<
0.1%).
Multiple Rate Considerations
R
establishes the fractional loop bandwidth. For a fixed
value of R
, f
will vary with the selected data rate. The
location of the critical frequencies f
Z
and f
P
, however, are in-
dependent of data rate.
To control jitter peaking for all multi-rate application choose:
the value of C
for the smallest value of f
BW
(which is ob-
tained at the lowest data rate).
the value of C
for the largest value of f
BW
(which is ob-
tained at the highest data rate).
Loop Filter Element Summary Table
The table below summarizes the recommended loop filter el-
ement values for each of the four SMPTE 259M data rates
and a fractional loop bandwidth of 0.25%. The final row of
the table gives the recommended values for the multi-rate
case, where all four of the SMPTE rates are configured.
Data Rate
(Mbps)
143
177
270
360
143–360
f
BW
(kHz)
358
443
675
900
R
BW
(
)
500
500
500
500
500
C
Z
(μF)
0.10
0.10
0.047
0.04
0.10
C
P
(pF)
200
160
100
82
82
0.25% f
CLK
Component Types and Tolerances
It is recommended that R
BW
resistors have tolerances of 1%
and temperature coefficients of
≤
100 ppm/C. The recom-
mended capacitors are ceramic surface mount with 5% toler-
ance or better.
AUTO-RATE SELECTION
Auto Rate Mode (ARM)
This section provides more detail on the ARS sub-system
and how to use it. Figure 7shows a detailed view of the ARS
portion of the Figure 3 block diagram
The auto-rate mode is enabled by connecting AUTO to V
and SER to ACQ/WR through the 1 k
/1 nF network. When
the VCO is not at the input data rate, SER goes high en-
abling the ARS oscillator and the Latch. The oscillator incre-
ments the 2-bit counter and causes the VCO to sequence
through the rates determined by resistor R
(beginning at the
currently selected rate and advancing the index, n, upward).
The oscillator period (T
) is determined by C
. When
the VCO rate is at the input data rate, SER goes low and
ceases to increment the counter.
DS100087-18
FIGURE 6. Jitter Peaking Curve
C
www.national.com
11
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLC016_02 | 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:Data Retiming PLL with Automatic Rate Selection |
| CLC016ACQ | 制造商:Texas Instruments 功能描述:Data Retiming PLL w/Auto Rate,CLC016ACQ |
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| CLC016AJQ | 制造商:Texas Instruments 功能描述:Data Retiming PLL w/Auto Rate,CLC016AJQ |
| CLC016AJQ | 制造商:Texas Instruments 功能描述:IC DATA RETIMING PLL SMD PLCC28 |
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