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參數(shù)資料
| 型號： | CLC016 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Data Retiming PLL with Automatic Rate Selection(帶自動速率選擇的數(shù)據(jù)重定時PLL) |
| 中文描述： | 數(shù)據(jù)定時鎖相環(huán)（帶自動速率選擇的數(shù)據(jù)重定時鎖相環(huán)），具有自動速率選擇 |
| 文件頁數(shù)： | 15/20頁 |
| 文件大小： | 435K |
| 代理商： | CLC016 |
Product Description
(Continued)
CONTROL LINE INTERFACES
The use of the CLC016 with +5V supplies allows the control
lines to interface to standard TTL logic signals. Operating the
CLC016 at 5.2V requires level-shifting circuits for the con-
trol line inputs. Refer to the
Static Performance
section of
the
Electrical Characteristics
page for required input volt-
age levels.
POWER CONSUMPTION
The power supply current given in the Electrical Characteris-
tics table includes the current required for both the clock and
data output buffers to drive a 75
load to ECL swings.
TYPICAL APPLICATIONS
The CLC016 was designed as one of a series of data trans-
mission support chips. The CLC016 is recommended for a
wide variety of clock and data recovery applications that fit
within its range of data rates.
Serial Data Transmission over Cable
Serial data transmission is common for all types of commu-
nication channels where the data is sent over coaxial or
twisted pair cable. Figure 21 shows a typical connection us-
ing a CLC006 driver chip, CLC014Adaptive Cable Equalizer,
and the CLC016 Data Retiming PLL. The CLC016 extracts
the clock and retimes the data from the serial bit stream.
The components recommended in Figure 21 support the
four common data rates specified in SMPTE 259M.
ESD
The CLC016 is a
CMOS chip.
Operators are cautioned to
use grounding straps when handling.
MEASUREMENTS & EVALUATION
When evaluating the CLC016 Data Retimer, it is recom-
mended that you solder the part to the board or use a lead-
less chip carrier socket. Probing with capacitive probes will
disturb the CLC016 performance. When probing the signal
levels use a
1 pF capacitance
probe with a 500
tip.
The block diagram below shows a simple method of measur-
ing the clock to eye pattern jitter. Use of the CLC016 evalu-
ation board is recommended for jitter evaluation. It also pro-
vides a good reference for a user’s circuit board design. The
plot in Figure 23 shows a histogram of the jitter and where
the measurements were taken.
DS100087-32
FIGURE 20. Load Terminated Output Interface
DS100087-33
FIGURE 21. Typical Cable Connection
C
www.national.com
15
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLC016_02 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Data Retiming PLL with Automatic Rate Selection |
| CLC016ACQ | 制造商:Texas Instruments 功能描述:Data Retiming PLL w/Auto Rate,CLC016ACQ |
| CLC016ACQ/NOPB | 功能描述:IC DATA RETIMING PLL 28-PLCC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| CLC016AJQ | 制造商:Texas Instruments 功能描述:Data Retiming PLL w/Auto Rate,CLC016AJQ |
| CLC016AJQ | 制造商:Texas Instruments 功能描述:IC DATA RETIMING PLL SMD PLCC28 |
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