- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379893 > CLC016 (National Semiconductor Corporation) Data Retiming PLL with Automatic Rate Selection(帶自動速率選擇的數(shù)據(jù)重定時PLL) PDF資料下載
參數(shù)資料
| 型號： | CLC016 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Data Retiming PLL with Automatic Rate Selection(帶自動速率選擇的數(shù)據(jù)重定時PLL) |
| 中文描述： | 數(shù)據(jù)定時鎖相環(huán)（帶自動速率選擇的數(shù)據(jù)重定時鎖相環(huán)），具有自動速率選擇 |
| 文件頁數(shù)： | 10/20頁 |
| 文件大?。?/td> | 435K |
| 代理商： | CLC016 |
Product Description
(Continued)
The jitter transfer function is the small signal transfer func-
tion,
θ
o
/
θ
i
, and is given by:
where f
is the PLL bandwidth and f
Z
is a zero in the closed
loop transfer function.
The phase detector gain and VCO gain are fixed internally.
Selection of the external loop filter components defines the
overall jitter transfer function. Additionally, the filter compo-
nents control the acquisition performance of the PLL.
A Bode plot for the closed loop PLL jitter transfer function is
shown in Figure 5
At frequencies above f
(the PLL bandwidth) the jitter is at-
tenuated. At frequencies below f
the jitter is transmitted
through the PLL. A small amount of jitter peaking (
δ
) occurs
at frequencies below f
. The amount of peaking increases
when f
Z
moves closer to f
BW
.
Setting the Loop Bandwidth (Selecting R
BW
)
The fractional loop bandwidth,
λ
BW
, is the ratio of f
BW
to the
data rate. The CLC016 is specified for operation with frac-
tional loop bandwidths ranging from 0.05% to 0.5%. For ex-
ample, if the loop bandwidth is 1 MHz and the data rate is
270 Mbps, then the fractional loop bandwidth is:
The fractional loop bandwidth is set by the loop component
R
BW
:
where
ρ
is the data transition density in average number of
data transitions per bit cell, and ranges in value from 0 to 1.
For example, if a pseudo-random data stream is used, the
value of
ρ
is 1/2, and a data transition will occur once every
two bit cells on the average. The phase detector and VCO
gain set the constants in the equation.
If the value of R
BW
is 500
and
ρ
= 1/2, the fractional loop
bandwidth is:
For a data rate of 270 Mbps this corresponds to a loop band-
width f
BW
= 644 kHz. The jitter at frequencies above 644 kHz
will be attenuated by the PLL.
The equation may be rearranged to obtain R
BW
as a function
of the desired fractional loop bandwidth:
Setting the Jitter Peaking Factor (Selecting C
Z
)
The jitter peaking factor,
δ
, is set by the ratio of the critical
frequencies f
Z
and f
BW
. The ratio is defined as:
Figure 6 shows how the jitter peaking factor,
δ
, varies with
α
.
For example, if the value of
α
is 0.1, then the jitter peaking is
about 0.6 dB.
The approximation for the required value of
α
to obtain a
given amount of jitter peaking is:
α
.
δ
(0.134 + 0.058
δ
)
The critical frequency f
Z
is:
Select C
Z
by the following equation:
DS100087-16
FIGURE 4. PLL Loop
DS100087-17
FIGURE 5. Closed-Loop Transfer Function
C
www.national.com
10
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CLC018AJVJQ | Circular Connector; No. of Contacts:41; Series:MS27473; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:20; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:20-41 RoHS Compliant: No |
| CLC018 | 8 x 8 Digital Crosspoint Switch, 1.4 Gbps(8 x 8數(shù)字交點開關(guān)，1.4 Gbps) |
| CLC020BCQ | SMPTE 259M Digital Video Serializer with Integrated Cable Driver |
| CLC020 | SMPTE 259M Digital Video Serializer with Integrated Cable Driver(SMPTE 259M數(shù)字視頻串行器帶集成電纜驅(qū)動器) |
| CLC020ACQ | SMPTE 259M Digital Video Serializer with Integrated Cable Driver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLC016_02 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Data Retiming PLL with Automatic Rate Selection |
| CLC016ACQ | 制造商:Texas Instruments 功能描述:Data Retiming PLL w/Auto Rate,CLC016ACQ |
| CLC016ACQ/NOPB | 功能描述:IC DATA RETIMING PLL 28-PLCC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| CLC016AJQ | 制造商:Texas Instruments 功能描述:Data Retiming PLL w/Auto Rate,CLC016AJQ |
| CLC016AJQ | 制造商:Texas Instruments 功能描述:IC DATA RETIMING PLL SMD PLCC28 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。