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參數(shù)資料
| 型號(hào)： | CLC016 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Data Retiming PLL with Automatic Rate Selection(帶自動(dòng)速率選擇的數(shù)據(jù)重定時(shí)PLL) |
| 中文描述： | 數(shù)據(jù)定時(shí)鎖相環(huán)（帶自動(dòng)速率選擇的數(shù)據(jù)重定時(shí)鎖相環(huán)），具有自動(dòng)速率選擇 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 435K |
| 代理商： | CLC016 |
Product Description
(Continued)
SER goes high when CD is high and either of the following
conditions is true:
The FD is active, causing LHP to go high.
The harmonic lock detector determines that the VCO is
running at a harmonic of the input data rate, causing
HLOCK to go high.
Timing diagrams related to locking and unlocking of the PLL
and removal of the input data are given in Figures 8, 9 and
Figure 10 The term t
in Figure 8 is defined in the
Loop
Filter Design
section. Also, t
is the settling time for the
phase error to decay to less than 90. It is given by the fol-
lowing equation:
t
S
= R
BW
x C
Z
x In(2) + 20 μs
The ARS oscillator period must be greater than the sum of t
ACQ
and t
S
:
t
ARS
= (140 ms/μF) x C
ARS
>
t
ACQ
+ t
S
The harmonic lock detector senses if the VCO is locked to a
data rate harmonic (integer multiple) by looking for the pres-
ence of bit changes across 3 consecutive periods of CLK as
shown in Case 1 of Figure 11 This event occurs on average
25% of the time in random data. HLOCK goes low if the oc-
currence rate is less than 12.5%. When a harmonic lock con-
dition occurs there is at least a 2 μs delay for HLOCK to go
high. Case 2 illustrates the situation where CLK is at the 2nd
harmonic of the input data rate and each input bit cell is
double-clocked. Bit changes across three consecutive peri-
ods are never detected and HLOCK goes high.
During intervals of sparse data transitions, the harmonic lock
detector may cause SER to go high. An example of this is
the pathological pattern associated with the SMPTE 259M
video industry standard. For an interval of 50 μs, the input
data transitions can be separated by 20-bit cells; and it ap-
pears to the harmonic lock detector as though the VCO is at
a harmonic rate. So long as these intervals do not exceed
the period of the ARS oscillator, the ARS sub-system will not
increment the 2-bit counter.
T
must be the greater of
the value calculated by the above equation of the sparse
data pattern interval.
Figure 12 shows a timing diagram re-
lating to sparse data transition intervals.
In auto-rate mode the user can monitor the RD0/1 bus to de-
termine the automatically selected data rate. Refer to Table 3
for the correspondence between the data bus state and the
selected rate resistor.
DS100087-19
FIGURE 7. Auto-Rate Select
DS100087-20
FIGURE 8. Data Rate Applied or Moves
within PLL Capture
DS100087-21
FIGURE 9. Data Rate Moves beyond the
PLL Tracking Range
DS100087-22
FIGURE 10. Input Data Removed
DS100087-23
FIGURE 11. Harmonic Lock Detector Operation
C
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLC016_02 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Data Retiming PLL with Automatic Rate Selection |
| CLC016ACQ | 制造商:Texas Instruments 功能描述:Data Retiming PLL w/Auto Rate,CLC016ACQ |
| CLC016ACQ/NOPB | 功能描述:IC DATA RETIMING PLL 28-PLCC RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| CLC016AJQ | 制造商:Texas Instruments 功能描述:Data Retiming PLL w/Auto Rate,CLC016AJQ |
| CLC016AJQ | 制造商:Texas Instruments 功能描述:IC DATA RETIMING PLL SMD PLCC28 |
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