參數(shù)資料
型號(hào)： CL-PS6700-VC-A
廠(chǎng)商： CIRRUS LOGIC INC
元件分類(lèi)： 總線(xiàn)控制器
英文描述： Low-Power PC Card Controller for the CL-PS7111
中文描述： PCMCIA BUS CONTROLLER, PQFP100
封裝： PLASTIC, VQFP-100
文件頁(yè)數(shù)： 27/48頁(yè)
文件大?。?/td> 562K
代理商： CL-PS6700-VC-A
November 1997
27
PRELIMINARY DATA BOOK v1.0
REGISTERS
C
I R R U S
L
O G I C
C
O N F I D E N T I A L
, N D A R
E Q U I R E D
CL-PS6700
Low-Power PC Card Controller
4.4.2
DMA Control Register
(0X0C004000
)
4.4.3
Device Information Register
(0X0C004400
)
Bit(s)
Description
Default R/W
15:9
Reserved
–
–
8
Enable Handshake with CL-PS7111 Using PDREQ_L.
If this bit is cleared, then PDREQ_L
is always deasserted. If Power Management register bit 7 is set, then this bit is a don’t care
0
R/W
7
Card DMA Enable.
Enables card DMA transfer. A DMA transfer is defined by REG_L deas-
serted and IORD_L or IOWR_L asserted. OE_L and WE_L indicate the terminal count for read
and write, respectively.
0
R/W
6:4
DMA Request Input Select.
Selects input to be used for DMA handshake between the
CL-PS6700 and the card. Currently, there is no dedicated card pin assigned for DMA request.
000 – Disable DMA access
001 – PCTL[2]
010 – PCM_VS[2]
011 – Reserved
101 – PCM_WP input
110 – PCM_BVD2
111 – Card always requesting DMA transfer (no handshake between CL-PS6700 and card).
After each DMA transfer from CL-PS7111 to CL-PS6700, PDREQ_L is immediately
reasserted.
000
R/W
3
DMA Request Polarity Select.
If this bit is set, the selected DMA request input (as described
above) is inverted to be active-low.
0
R/W
2
Transparent DMA Request.
If this bit is set, then external DMA request input is passed
through to the PDREQ_L output after being synchronized to PCLK.
0
R/W
1
CPU Initiated DMA.
This allows the CPU to generate a card DMA transfer. If this bit is set, a
CPU access to I/O space is converted to a DMA transfer. REG_L is kept high (deasserted),
and IORD_L or IOWR_L is used to transfer data.
0
R/W
0
CPU Initiated DMA with Terminal Count.
If this bit is set, a CPU access to I/O space is con-
verted to a DMA transfer. REG_L is kept high (deasserted). The end of DMA is indicated to the
card by OE_L low (read) or WE_L low (write). IORD_L or IOWR_L are used to transfer data.
0
R/W
Bit(s)
Description
Default R/W
7:6
Chip ID
01
R
5
Dual/Single Socket.
Single-socket device if low.
0
R
4:2
Revision Level.
This changes as new revisions become available.
00
R
1:0
Reserved
00
R
相關(guān)PDF資料
PDF描述
CL-PS7110-VC-A Low-Power System-on-a-Chip
CL-PS7110-VI-A Low-Power System-on-a-Chip
CL-PS7110 Low-Power System-on-a-Chip
CL-PS7111 Low-Power System-on-a-Chip
CL-PS7111-VC-A Low-Power System-on-a-Chip
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CL-PS7110 制造商:CIRRUS 制造商全稱(chēng):Cirrus Logic 功能描述:Low-Power System-on-a-Chip
CL-PS7110-VC-A 制造商:CIRRUS 制造商全稱(chēng):Cirrus Logic 功能描述:Low-Power System-on-a-Chip
CL-PS7110-VI-A 制造商:CIRRUS 制造商全稱(chēng):Cirrus Logic 功能描述:Low-Power System-on-a-Chip
CL-PS7111 制造商:CIRRUS 制造商全稱(chēng):Cirrus Logic 功能描述:Low-Power System-on-a-Chip
CL-PS7111(208LQFP) 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Logic IC
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