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參數(shù)資料
| 型號： | CL-PS6700-VC-A |
| 廠商： | CIRRUS LOGIC INC |
| 元件分類： | 總線控制器 |
| 英文描述： | Low-Power PC Card Controller for the CL-PS7111 |
| 中文描述： | PCMCIA BUS CONTROLLER, PQFP100 |
| 封裝： | PLASTIC, VQFP-100 |
| 文件頁數(shù)： | 14/48頁 |
| 文件大?。?/td> | 562K |
| 代理商： | CL-PS6700-VC-A |
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PRELIMINARY DATA BOOK v1.0
November 1997
14
PIN DESCRIPTIONS
C
I R R U S
L
O G I C
C
O N F I D E N T I A L
, N D A R
E Q U I R E D
CL-PS6700
Low-Power PC Card Controller
2.2
PC Card Interface Signals
A PC Card socket can be configured as either memory onlyor combined I/O-memory Some pins on the
PC Card interface have different meanings in memory and I/O modes. These pins are listed as dual-mode.
The mode is selected by a configuration register bit. When I/O mode is programmed, the CPU accesses
either I/O space or memory space on the card according to the upper address bits. The CPU Attribute
memory is accessible in either memory or I/O modes, again, selected by the upper address bits. A card
DMA device is accessible only in I/O mode.
2.2.1
Address and Data Signals
Signal
Type
Power
SourceDescription
PCM_D[15:0]
I/O
pcm
PC Card data bus:
Single-mode. Data transfer can be either byte or half-word (16-bit) as con-
figured by the CPU. All byte accesses are transferred through their natural byte lane only (odd
bytes on PCM_D[15:8] and even bytes on PCM_D[7:0]).
PCM_A[25:0]
O
pcm
PC Card address bus:
Single-mode. This is a byte address during byte operations and a half-
word address during half-word (16-bit) accesses (that is, A[0] is kept low).
2.2.2
Access Control Signals
Signal
Type
Power
SourceDescription
PCM_CE_L[2:1]
O
pcm
Card enables:
Single-mode. These are the byte enable lines for the data bus.
PCM_CE_L[1] enables even bytes, D[7:0], and PCM_CE_L[2] enables odd bytes, D[15:8].
PCM_OE_L
O
pcm
Output enable for memory read data.
Single-mode. PCM_OE_L enables the card’s data
outputs. During a write operation, this signal is deasserted (high). During a card read DMA
transfer, this signal is used as a terminal count and is asserted along with PCM_IORD_L
during the last DMA card read.
PCM_WE_L
O
pcm
Write enable signal for common memory and DMA:
Single-mode. During a card write
DMA transfer, this signal is used as a terminal count and is asserted along with
PCM_IOWR_L during the last DMA card write.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CL-PS7110-VC-A | Low-Power System-on-a-Chip |
| CL-PS7110-VI-A | Low-Power System-on-a-Chip |
| CL-PS7110 | Low-Power System-on-a-Chip |
| CL-PS7111 | Low-Power System-on-a-Chip |
| CL-PS7111-VC-A | Low-Power System-on-a-Chip |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CL-PS7110 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Low-Power System-on-a-Chip |
| CL-PS7110-VC-A | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Low-Power System-on-a-Chip |
| CL-PS7110-VI-A | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Low-Power System-on-a-Chip |
| CL-PS7111 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Low-Power System-on-a-Chip |
| CL-PS7111(208LQFP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
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