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參數(shù)資料
| 型號： | CDP1802A |
| 廠商： | Intersil Corporation |
| 元件分類： | 8位微控制器 |
| 英文描述： | CMOS 8-Bit Microprocessors |
| 中文描述： | 的CMOS 8位微處理器 |
| 文件頁數(shù)： | 24/27頁 |
| 文件大?。?/td> | 115K |
| 代理商： | CDP1802A |
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NOTES: (For Table 1)
1. The arithmetic operations and the shift instructions are the only instructions that can alter the DF.
After an add instruction:
DF = 1 denotes a carry has occurred
DF = 0 Denotes a carry has not occurred
After a subtract instruction:
DF = 1 denotes no borrow. D is a true positive number
DF = 0 denotes a borrow. D is two’s complement
The syntax “-(not DF)” denotes the subtraction of the borrow.
2. This instruction is associated with more than one mnemonic. Each mnemonic is individually listed.
3. An idle instruction initiates a repeating S1 cycle. The processor will continue to idle until an I/O request (INTERRUPT, DMA-lN, or DMA- OUT) is
activated. When the request is acknowledged, the idle cycle is terminated and the I/O request is serviced, and then normal operation is resumed.
4. Long-Branch, Long-Skip and No Op instructions require three cycles to complete (1 fetch + 2 execute).
Long-Branch instructions are three bytes long. The first byte specifies the condition to be tested; and the second and third byte, the
branching address.
The long-branch instructions can:
a.
Branch unconditionally
b.
Test for D = 0 or D
≠
0
c.
Test for DF = 0 or DF = 1
d.
Test for Q = 0 or Q = 1
e.
Effect an unconditional no branch
If the tested condition is met, then branching takes place; the branching address bytes are loaded in the high-and-low order bytes of the
current program counter, respectively. This operation effects a branch to any memory location.
If the tested condition is not met, the branching address bytes are skipped over, and the next instruction in sequence is fetched and exe-
cuted. This operation is taken for the case of unconditional no branch (NLBR).
5. The short-branch instructions are two bytes long. The first byte specifies the condition to be tested, and the second specifies the branching address.
The short branch instruction can:
a.
Branch unconditionally
b.
Test for D = 0 or D
≠
0
c.
Test for DF = 0 or DF = 1
d.
Test for Q = 0 or Q = 1
e.
Test the status (1 or 0) of the four EF flags
f.
Effect an unconditional no branch
If the tested condition is met, then branching takes place; the branching address byte is loaded into the low-order byte position of the
current program counter. This effects a branch within the current 256-byte page of the memory, i.e., the page which holds the branching
address. If the tested condition is not met, the branching address byte is skipped over, and the next instruction in sequence is fetched
and executed. This same action is taken in the case of unconditional no branch (NBR).
6. The skip instructions are one byte long. There is one Unconditional Short-Skip (SKP) and eight Long-Skip instructions.
The Unconditional Short-Skip instruction takes 2 cycles to complete (1 fetch + 1 execute). Its action is to skip over the byte following it.
Then the next instruction in sequence is fetched and executed. This SKP instruction is identical to the unconditional no-branch instruc-
tion (NBR) except that the skipped-over byte is not considered part of the program.
The Long-Skip instructions take three cycles to complete (1 fetch + 2 execute).
They can:
a.
Skip unconditionally
b.
Test for D = 0 or D
≠
0
c.
Test for DF = 0 or DF = 1
d.
Test for Q = 0 or Q = 1
e.
Test for IE = 1
If the tested condition is met, then Long Skip takes place; the current program counter is incremented twice. Thus two bytes are skipped
over, and the next instruction in sequence is fetched and executed. If the tested condition is not met, then no action is taken. Execution
is continued by fetching the next instruction in sequence.
TABLE 1. INSTRUCTION SUMMARY
(SEE NOTES)
(Continued)
INSTRUCTION
MNEMONIC
OP
CODE
OPERATION
CDP1802A, CDP1802AC, CDP1802BC
相關PDF資料 |
PDF描述 |
|---|---|
| CDP1805 | CMOS 8-Bit Microprocessor with On-Chip RAM and Counter/Timer |
| CDP1805AC | CMOS 8-Bit Microprocessor with On-Chip RAM and Counter/Timer |
| CDP1805ACD | CMOS 8-Bit Microprocessor with On-Chip RAM and Counter/Timer |
| CDP1805ACDX | CMOS 8-Bit Microprocessor with On-Chip RAM and Counter/Timer |
| CDP1805ACE | CMOS 8-Bit Microprocessor with On-Chip RAM and Counter/Timer |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CDP1802A_1 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 8-Bit Microprocessors |
| CDP1802AC | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High-Reliability CMOS 8-Bit Microprocessor |
| CDP1802AC/3 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High-Reliability CMOS 8-Bit Microprocessor |
| CDP1802AC3 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High-Reliability CMOS 8-Bit Microprocessor |
| CDP1802ACD | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 8-Bit Microprocessors |
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