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參數(shù)資料
| 型號： | CDP1802A |
| 廠商： | Intersil Corporation |
| 元件分類： | 8位微控制器 |
| 英文描述： | CMOS 8-Bit Microprocessors |
| 中文描述： | 的CMOS 8位微處理器 |
| 文件頁數(shù)： | 23/27頁 |
| 文件大?。?/td> | 115K |
| 代理商： | CDP1802A |
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3-25
LONG BRANCH lF Q = 0
LBNQ
C9
lF Q = 0, M(R(P))
→
R(P).1, M(R(P) + 1)
→
R(P).0
EISE R(P) + 2
→
R(P)
SKIP INSTRUCTIONS
SHORT SKIP (See NBR)
SKP
38
(Note 2)
R(P) + 1
→
R(P)
LONG SKIP (See NLBR)
LSKP
C8
(Note 2)
R(P) + 2
→
R(P)
LONG SKIP IF D = 0
LSZ
CE
IF D = 0, R(P) + 2
→
R(P), ELSE CONTINUE
LONG SKIP IF D NOT 0
LSNZ
C6
IF D Not 0, R(P) + 2
→
R(P), ELSE CONTINUE
LONG SKIP IF DF = 1
LSDF
CF
IF DF = 1, R(P) + 2
→
R(P), ELSE CONTINUE
LONG SKIP IF DF = 0
LSNF
C7
IF DF = 0, R(P) + 2
→
R(P), ELSE CONTINUE
LONG SKIP lF Q = 1
LSQ
CD
IF Q = 1, R(P) + 2
→
R(P), ELSE CONTINUE
LONG SKIP IF Q = 0
LSNQ
C5
IF Q = 0, R(P) + 2
→
R(P), ELSE CONTINUE
LONG SKIP IF lE = 1
LSlE
CC
IF IE = 1, R(P) + 2
→
R(P), ELSE CONTINUE
CONTROL INSTRUCTIONS
IDLE
lDL
00
(Note 3)
WAIT FOR DMA OR INTERRUPT; M(R(0))
→
BUS
NO OPERATION
NOP
C4
CONTINUE
SET P
SEP
DN
N
→
P
SET X
SEX
EN
N
→
X
SET Q
SEQ
7B
1
→
Q
RESET Q
REQ
7A
0
→
Q
SAVE
SAV
78
T
→
M(R(X))
PUSH X, P TO STACK
MARK
79
(X, P)
→
T; (X, P)
→
M(R(2)), THEN P
→
X; R(2) - 1
→
R(2)
RETURN
RET
70
M(R(X))
→
(X, P); R(X) + 1
→
R(X), 1
→
lE
DISABLE
DlS
71
M(R(X))
→
(X, P); R(X) + 1
→
R(X), 0
→
lE
INPUT - OUTPUT BYTE TRANSFER
OUTPUT 1
OUT 1
61
M(R(X))
→
BUS; R(X) + 1
→
R(X); N LINES = 1
OUTPUT 2
OUT 2
62
M(R(X))
→
BUS; R(X) + 1
→
R(X); N LINES = 2
OUTPUT 3
OUT 3
63
M(R(X))
→
BUS; R(X) + 1
→
R(X); N LINES = 3
OUTPUT 4
OUT 4
64
M(R(X))
→
BUS; R(X) + 1
→
R(X); N LINES = 4
OUTPUT 5
OUT 5
65
M(R(X))
→
BUS; R(X) + 1
→
R(X); N LINES = 5
OUTPUT 6
OUT 6
66
M(R(X))
→
BUS; R(X) + 1
→
R(X); N LINES = 6
OUTPUT 7
OUT 7
67
M(R(X))
→
BUS; R(X) + 1
→
R(X); N LINES = 7
INPUT 1
INP 1
69
BUS
→
M(R(X)); BUS
→
D; N LINES = 1
INPUT 2
INP 2
6A
BUS
→
M(R(X)); BUS
→
D; N LINES = 2
INPUT 3
INP 3
6B
BUS
→
M(R(X)); BUS
→
D; N LINES = 3
INPUT 4
INP 4
6C
BUS
→
M(R(X)); BUS
→
D; N LINES = 4
INPUT 5
INP 5
6D
BUS
→
M(R(X)); BUS
→
D; N LINES = 5
INPUT 6
INP 6
6E
BUS
→
M(R(X)); BUS
→
D; N LINES = 6
INPUT 7
INP 7
6F
BUS
→
M(R(X)); BUS
→
D; N LINES = 7
TABLE 1. INSTRUCTION SUMMARY
(SEE NOTES)
(Continued)
INSTRUCTION
MNEMONIC
OP
CODE
OPERATION
CDP1802A, CDP1802AC, CDP1802BC
相關PDF資料 |
PDF描述 |
|---|---|
| CDP1805 | CMOS 8-Bit Microprocessor with On-Chip RAM and Counter/Timer |
| CDP1805AC | CMOS 8-Bit Microprocessor with On-Chip RAM and Counter/Timer |
| CDP1805ACD | CMOS 8-Bit Microprocessor with On-Chip RAM and Counter/Timer |
| CDP1805ACDX | CMOS 8-Bit Microprocessor with On-Chip RAM and Counter/Timer |
| CDP1805ACE | CMOS 8-Bit Microprocessor with On-Chip RAM and Counter/Timer |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CDP1802A_1 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 8-Bit Microprocessors |
| CDP1802AC | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High-Reliability CMOS 8-Bit Microprocessor |
| CDP1802AC/3 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High-Reliability CMOS 8-Bit Microprocessor |
| CDP1802AC3 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High-Reliability CMOS 8-Bit Microprocessor |
| CDP1802ACD | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 8-Bit Microprocessors |
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