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參數(shù)資料
| 型號： | CDP1802A |
| 廠商： | Intersil Corporation |
| 元件分類： | 8位微控制器 |
| 英文描述： | CMOS 8-Bit Microprocessors |
| 中文描述： | 的CMOS 8位微處理器 |
| 文件頁數(shù)： | 19/27頁 |
| 文件大?。?/td> | 115K |
| 代理商： | CDP1802A |
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3-21
isters in R can be used as subroutine program counters. By
single instruction the contents of the P register can be
changed to effect a “call” to a subroutine. When interrupts
are being serviced, register R(1) is used as the program
counter for the user's interrupt servicing routine. After reset,
and during a DMA operation, R(0) is used as the program
counter. At all other times the register designated as pro-
gram counter is at the discretion of the user.
Data Pointers
The registers in R may be used as data pointers to indicate a
location in memory. The register designated by X (i.e., R(X))
points to memory for the following instructions (see Table 1).
1. ALU operations F1 - F5, F7, 74, 75, 77
2. Output instructions 61 through 67
3. Input instructions 69 through 6F
4. Certain miscellaneous instructions - 70 - 73, 78, 60, F0
The register designated by N (i.e., R(N)) points to memory
for the “l(fā)oad D from memory” instructions 0N and 4N and the
“Store D” instruction 5N. The register designated by P (i.e.,
the program counter) is used as the data pointer for ALU
instructions F8 - FD, FF, 7C, 7D, 7F. During these instruction
executions, the operation is referred to as “data immediate”.
Another important use of R as a data pointer supports the
built-in Direct-Memory-Access (DMA) function. When a
DMA-ln or DMA-Out request is received, one machine cycle
is “stolen”. This operation occurs at the end of the execute
machine cycle in the current instruction. Register R(0) is
always used as the data pointer during the DMA operation.
The data is read from (DMA-Out) or written into (DMA-ln) the
memory location pointed to by the R(0) register. At the end
of the transfer, R(0) is incremented by one so that the pro-
cessor is ready to act upon the next DMA byte transfer
request. This feature in the 1800-series architecture saves a
substantial amount of logic when fast exchanges of blocks of
data are required, such as with magnetic discs or during
CRT-display-refresh cycles.
Data Registers
When registers in R are used to store bytes of data, four
instructions are provided which allow D to receive from or
write into either the higher-order or lower-order byte portions
of the register designated by N. By this mechanism (together
with loading by data immediate) program pointer and data
pointer designations are initialized. Also, this technique
allows scratchpad registers in R to be used to hold general
data. By employing increment or decrement instructions,
such registers may be used as loop counters.
The Q Flip-Flop
An internal flip-flop, Q, can be set or reset by instruction and
can be sensed by conditional branch instructions. The output
of Q is also available as a microprocessor output.
Interrupt Servicing
Register R(1) is always used as the program counter when-
ever interrupt servicing is initiated. When an interrupt
request occurs and the interrupt is allowed by the program
(again, nothing takes place until the completion of the cur-
rent instruction), the contents of the X and P registers are
stored in the temporary register T, and X and P are set to
new values; hex digit 2 in X and hex digit 1 in P. Interrupt
Enable is automatically deactivated to inhibit further inter-
rupts. The user's interrupt routine is now in control; the con-
tents of T may be saved by means of a single instruction (78)
in the memory location pointed to by R(X). At the conclusion
of the interrupt, the user's routine may restore the pre-inter-
rupted value of X and P with a single instruction (70 or 71).
The Interrupt Enable flip-flop can be activated to permit fur-
ther interrupts or can be disabled to prevent them.
CPU Register Summary
CDP1802 Control Modes
The WAIT and CLEAR lines provide four control modes as
listed in the following truth table:
The function of the modes are defined as follows:
Load
Holds the CPU in the IDLE execution state and allows an I/O
device to load the memory without the need for a “bootstrap”
loader. It modifies the IDLE condition so that DMA-lN opera-
tion does not force execution of the next instruction.
Reset
Registers l, N, Q are reset, lE is set and 0’s (VSS) are placed
on the data bus. TPA and TPB are suppressed while reset is
held and the CPU is placed in S1. The first machine cycle after
termination of reset is an initialization cycle which requires 9
clock pulses. During this cycle the CPU remains in S1 and reg-
ister X, P and R(0) are reset. Interrupt and DMA servicing are
D
8 Bits
Data Register (Accumulator)
DF
1-Bit
Data Flag (ALU Carry)
B
8 Bits
Auxiliary Holding Register
R
16 Bits
1 of 16 Scratchpad Registers
P
4 Bits
Designates which register is Program Counter
X
4 Bits
Designates which register is Data Pointer
N
4 Bits
Holds Low-Order Instruction Digit
I
4 Bits
Holds High-Order Instruction Digit
T
8 Bits
Holds old X, P after Interrupt (X is high nibble)
lE
1-Bit
Interrupt Enable
Q
1-Bit
Output Flip-Flop
CLEAR
WAIT
MODE
L
L
LOAD
L
H
RESET
H
L
PAUSE
H
H
RUN
CDP1802A, CDP1802AC, CDP1802BC
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| CDP1805 | CMOS 8-Bit Microprocessor with On-Chip RAM and Counter/Timer |
| CDP1805AC | CMOS 8-Bit Microprocessor with On-Chip RAM and Counter/Timer |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDP1802A_1 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 8-Bit Microprocessors |
| CDP1802AC | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High-Reliability CMOS 8-Bit Microprocessor |
| CDP1802AC/3 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High-Reliability CMOS 8-Bit Microprocessor |
| CDP1802AC3 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High-Reliability CMOS 8-Bit Microprocessor |
| CDP1802ACD | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 8-Bit Microprocessors |
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