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參數(shù)資料
| 型號： | CDP1802A |
| 廠商： | Intersil Corporation |
| 元件分類： | 8位微控制器 |
| 英文描述： | CMOS 8-Bit Microprocessors |
| 中文描述： | 的CMOS 8位微處理器 |
| 文件頁數(shù)： | 18/27頁 |
| 文件大小： | 115K |
| 代理商： | CDP1802A |
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3-20
MA0 to MA7 (8 Memory Address Lines)
In each cycle, the higher-order byte of a 16-bit CPU memory
address appears on the memory address lines MA0-7 first.
Those bits required by the memory system can be strobed
into external address latches by timing pulse TPA. The low
order byte of the 16-bit address appears on the address lines
after the termination of TPA. Latching of all 8 higher-order
address bits would permit a memory system of 64K bytes.
MWR (Write Pulse)
A negative pulse appearing in a memory-write cycle, after
the address lines have stabilized.
MRD (Read Level)
A low level on MRD indicates a memory read cycle. It can be
used to control three-state outputs from the addressed mem-
ory which may have a common data input and output bus. If a
memory does not have a three-state high-impedance output,
MRD is useful for driving memory/bus separator gates. It is
also used to indicate the direction of data transfer during an
I/O instruction. For additional information see Table 1.
Q
Single bit output from the CPU which can be set or reset
under program control. During SEQ or REQ instruction exe-
cution, Q is set or reset between the trailing edge of TPA and
the leading edge of TPB.
CLOCK
Input for externally generated single-phase clock. The clock is
counted down internally to 8 clock pulses per machine cycle.
XTAL
Connection to be used with clock input terminal, for an exter-
nal crystal, if the on-chip oscillator is utilized. The crystal is
connected between terminals 1 and 39 (CLOCK and XTAL)
in parallel with a resistance (10M
typ). Frequency trimming
capacitors may be required at terminals 1 and 39. For addi-
tional information, see Application Note AN6565.
WAIT, CLEAR (2 Control Lines)
Provide four control modes as listed in the following truth table:
V
DD
, V
SS
, V
CC
(Power Levels)
The internal voltage supply V
DD
is isolated from the
Input/Output voltage supply V
CC
so that the processor may
operate at maximum speed while interfacing with peripheral
devices operating at lower voltage. V
CC
must be less than or
equal to V
DD
. All outputs swing from V
SS
to V
CC
. The recom-
mended input voltage swing is V
SS
to V
CC
.
Architecture
The CPU block diagram is shown in Figure 2. The principal
feature of this system is a register array (R) consisting of six-
teen 16-bit scratchpad registers. Individual registers in the
array (R) are designated (selected) by a 4-bit binary code
from one of the 4-bit registers labeled N, P and X. The con-
tents of any register can be directed to any one of the follow-
ing three paths:
1. The external memory (multiplexed, higher-order byte first,
on to 8 memory address lines).
2. The D register (either of the two bytes can be gated to D).
3. The increment/decrement circuit where it is increased or
decreased by one and stored back in the selected 16-bit
register.
The three paths, depending on the nature of the instruction,
may operate independently or in various combinations in the
same machine cycle.
With two exceptions, CPU instruction consists of two 8-
clock-pulse machine cycles. The first cycle is the fetch cycle,
and the second - and third if necessary - are execute cycles.
During the fetch cycle the four bits in the P designator select
one of the 16 registers R(P) as the current program counter.
The selected register R(P) contains the address of the mem-
ory location from which the instruction is to be fetched.
When the instruction is read out from the memory, the higher
order 4 bits of the instruction byte are loaded into the register
and the lower order 4 bits into the N register. The content of
the program counter is automatically incremented by one so
that R(P) is now “pointing” to the next byte in the memory.
The X designator selects one of the 16 registers R(X) to
“point” to the memory for an operand (or data) in certain ALU
or I/O operations.
The N designator can perform the following five functions
depending on the type of instruction fetched:
1. Designate one of the 16 registers in R to be acted upon
during register operations.
2. Indicate to the I/O devices a command code or device
selection code for peripherals.
3. Indicate the specific operation to be executed during the
ALU instructions, types of test to be performed during the
Branch instruction, or the specific operation required in a
class of miscellaneous instructions (70 - 73 and 78 - 7B).
4. Indicate the value to be loaded into P to designate a new
register to be used as the program counter R(P).
5. Indicate the value to be loaded into X to designate a new
register to be used as data pointer R(X).
The registers in R can be assigned by a programmer in three
different ways: as program counters, as data pointers, or as
scratchpad locations (data registers) to hold two bytes of data.
Program Counters
Any register can be the main program counter; the address
of the selected register is held in the P designator. Other reg-
CLEAR
WAIT
MODE
L
L
LOAD
L
H
RESET
H
L
PAUSE
H
H
RUN
CDP1802A, CDP1802AC, CDP1802BC
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PDF描述 |
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| CDP1805 | CMOS 8-Bit Microprocessor with On-Chip RAM and Counter/Timer |
| CDP1805AC | CMOS 8-Bit Microprocessor with On-Chip RAM and Counter/Timer |
| CDP1805ACD | CMOS 8-Bit Microprocessor with On-Chip RAM and Counter/Timer |
| CDP1805ACDX | CMOS 8-Bit Microprocessor with On-Chip RAM and Counter/Timer |
| CDP1805ACE | CMOS 8-Bit Microprocessor with On-Chip RAM and Counter/Timer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDP1802A_1 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 8-Bit Microprocessors |
| CDP1802AC | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High-Reliability CMOS 8-Bit Microprocessor |
| CDP1802AC/3 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High-Reliability CMOS 8-Bit Microprocessor |
| CDP1802AC3 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High-Reliability CMOS 8-Bit Microprocessor |
| CDP1802ACD | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 8-Bit Microprocessors |
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