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參數資料
| 型號： | CDP1020 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | SMBus/I2C ACPI Dual Device Bay Controller |
| 中文描述： | I2C BUS CONTROLLER, PDSO28 |
| 封裝： | PLASTIC, MS-013AE, SOIC-28 |
| 文件頁數： | 6/23頁 |
| 文件大?。?/td> | 154K |
| 代理商： | CDP1020 |
2-423
Functional Pin Descriptions
This section provides a description of each of the 28 pins of
the CDP1020 as shown in Figure 2.
NOTE: The following pins are “5V Tolerant” Inputs at all Operating
Voltages: CLK, RESET, SCK, SDA, ALRT. This means that the input
voltages can range up to the maximum allowed (5V typical),
regardless of the operating voltage of the IC.
V
DD
, V
GATE
, V
LED
, and V
SS
(Power Supply)
Power is supplied to the CDP1020 using these pins. V
DD
is
connected to the positive logic supply (typically either 3.3V
or 5V), V
GATE
is connected to the positive supply for the
PWREN0 and PWREN1 gate drivers (typically 12V), V
LED
is
connected to the positive power supply for the LED drivers
(typically 5V), and V
SS
is connected to the negative supply
(Ground).
NOTE: V
GATE
and V
LED
power supplies should never be connected
to the CDP1020 without the presence of the V
DD
and V
SS
supplies.
Applying power to these inputs without the presence of the main
power supply could result in a condition where all level-shifted
outputs (PWRENx, LEDGx and LEDAx) track their power supply
input voltage, thus enabling any of their output circuitry.
RESET (Reset Input)
The RESET input is a low level active input, which resets the
CDP1020. Resetting the device forces ALRT high and forces
the device to reset the state of each bay (see
Effects Of
Reset
for more details). The RESET pin contains an internal
Schmitt Trigger to improve noise immunity.
1394PR0, 1394PR1, USBPR0, USBPR1
These four pins are the device presence inputs to the device
bay controller for both bay 0 (1394PR0 and USBPR0) and
bay 1 (1394PR1 and USBPR1). If the (peripheral) device
uses the 1394 or USB (or both), that pin(s) on its connector
is tied to GND (active low); when a device is inserted or
removed, these pins are monitored to reflect whether a
device is present (or not), and which of the two busses it
uses. All of these pins are CMOS inputs with internal active
pull-ups to V
DD
.
REMREQ0, REMREQ1
The REMREQ0 and REMREQ1 inputs are driven from the
“REMOVE REQUEST” buttons for bay 0 and bay 1,
respectively. These pins are CMOS inputs, with internal
active pull-ups to V
DD
.
SECURE0, SECURE1
SECURE0 and SECURE1 are inputs which are integral to
the bay security feature; each input should be connected
such that it will be asserted when an optional hardware lock
is engaged for the related bay. The state of these inputs are
observable by the operating system through the SL_STS
bits in the bay status registers. Both of these pins are CMOS
inputs with internal active pull-ups to V
DD
.
SDA (I
2
C/SMBus Data Input/Output)
The SDA pin is the serial data input to the SMBus interface
logic of the CDP1020; it contains an internal Schmitt Trigger
to improve noise immunity. When in slave-transmit mode,
this pin is an open drain output. Input thresholds for the SDA
input are fully compliant with SMBus Specification 1.0 (see
Electrical Specifications
). Refer to the
I
2
C/SMBus
Interface
text for more details.
SCK (I
2
C/SMBus Clock Input)
The SCK pin is the serial clock input to the SMBus interface
logic of the CDP1020; it contains an internal Schmitt Trigger
to improve noise immunity. Since the CDP1020 never acts
as a SMBus master, this pin is a dedicated clock input
(except for clock-stretching protocol, where it uses an open-
drain low-side output). Input thresholds for the SCK input are
fully compliant with SMBus Specification 1.0 (see
Electrical
Specifications
). Refer to the
I
2
C/SMBus Interface
text for
more details.
PWREN0, PWREN1
PWREN0 and PWREN1 are the outputs from the gate drive
level-shifter circuitry located on the CDP1020. These pins
will output V
GATE
(typically 12V) to drive the gates of the V
ID
control MOSFETs per Device Bay Specification 0.90.
SFTLOCK0, SFTLOCK1
SFTLOCK0 and SFTLOCK1 are CMOS outputs designed to
control the software locking mechanism installed in each
bay. These outputs are designed to drive solenoid driver
circuitry (such as an NFET), not a solenoid directly. The
output can be programmed via the Special Function Register
(SFR) to be a level or a pulse of a user defined duration.
Refer to the
Hardware
text for more details.
FIGURE 2. PINOUT DIAGRAM FOR THE CDP1020
LEDA1
REMREQ1
V
DD
LEDA0
LEDG0
SFTLOCK1
PWREN0
V
GATE
LEDG1
USBPR1
1394PR1
RESET
ALRT
SCK
SDA
USBPR0
1394PR0
SFTLOCK0
PWREN1
SECURE1
SECURE0
REMREQ0
V
LED
15
16
17
18
23
24
25
26
28
27
10
9
8
7
6
5
4
3
2
1
14
13
12
11
19
20
21
22
AD0
AD1
TEST (V
DD
)
V
SS
CLK
CDP1020
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相關代理商/技術參數 |
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| CDP1020M | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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| CDP1582EX | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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