參數(shù)資料
型號(hào)： CDP1020
廠商： INTERSIL CORP
元件分類： 總線控制器
英文描述： SMBus/I2C ACPI Dual Device Bay Controller
中文描述： I2C BUS CONTROLLER, PDSO28
封裝： PLASTIC, MS-013AE, SOIC-28
文件頁(yè)數(shù)： 14/23頁(yè)
文件大?。?/td> 154K
代理商： CDP1020
2-431
Special Function Register, $FC
The Special Function Register (SFR) allows control of
various features not explicitly defined in the Device Bay
Specification 0.90. This register contains write-once-only
bits, which are designed to be written by the system BIOS
immediately after power-on. Once written, they become
read-only. The upper 24 bits of the SFR are always read as
0. All bits are cleared on reset.
BITS 31:8
Reserved for future use. Always read as 0...
BITS 31:8
Reserved for future use. Always read as 0.
BITS 7:5, ITO[2:0]
Bits 7, 6 and 5 define the Insertion Time-Out (ITO) bits field
of the SFR.
These bits allow the OS/BIOS to specify the amount of time
the CDP1020 will wait, from when it detects the insertion of a
device until it notifies the OS. The insertion time-out should
be used to allow Device Bay devices time to settle
mechanically into the bay before they are enabled.
The 3-bit ITO field defines the time-out in 8 discrete increments
of 800ms (nominal at 4MHz). The table below shows typical
time-out values.
Please note that these time-out values do not account for
the fact that all presence inputs are debounced for 50ms
before any time-out period begins. The time-out defaults to
0 after reset.
SOL[3:0]
The SOL[3:0] bits, along with the SPD bit, control the
configuration and duration of the software lock solenoid drive
pulse. Once written to, these bits become read-only.
If %0000 is written to the SOL[3:0] bits, the solenoid output
is put into “l(fā)evel” mode. In level mode, the SFTLOCK output
simply follows the state of the corresponding LOCK_CTL bit
(see Figure 8).
If a nonzero value is written to the SOL[3:0] bits, then the
solenoid control output is put into “pulsed” mode. In this
mode, the solenoid output is pulsed anytime the LOCK_CTL
bit is written from a 1 to a 0 (refer to Figure 8). The length of
the pulse is determined by both the value written into the
SOL[3:0] bits and the SPD bit.
With the SPD bit clear, the solenoid control circuitry is set to
output short pulses. In terms of a prescaler, the solenoid
pulse width is the value of the SOL[3:0] x 50ms. With the
SPD bit set, the solenoid control is in long pulse mode. Here,
the prescaler is set to SOL[3:0] x 800ms. The table below
shows solenoid pulse widths for all values of SOL[3:0] and
the SPD bit.
NOTE: Writing to SOL[3:0] bits will clear all LOCK_CTL bits and
SFTLOCK outputs. Because these bits in the SFR are write-once-
only, this situation will only occur on the first write. Subsequent writes
to these bits will not cause the LOCK_CTL bits to clear
SPD
The SPD bit controls the length of the solenoid pulse when
in pulse mode: long pulses If set, short pulses If clear. If the
SOL[3:0] bits are clear, the SPD bit has no effect.
Bits 31:8
Bits 7:5
Bits 4:1
Bit 1
$000000
ITO[2:0]
SOL[3:0]
SPD
$FC
INSERTION TIME-OUT VALUES (NOMINAL AT 4MHz)
ITO[2:0]
TIME-OUT VALUE
000
0s
001
0.8s
010
1.6s
011
2.4s
100
3.2s
101
4.0s
110
4.8s
111
5.6s
SOLENOID PULSE WIDTHS (NOMINAL AT 4MHz)
SOL[3:0]
SOLENOID PULSE,
SPD = 0
SOLENOID PULSE,
SPD = 1
0000
LEVEL
LEVEL
0001
50ms
0.8ms
0010
100ms
1.6s
0011
150ms
2.4s
0100
200ms
3.2s
0101
250ms
4.0s
0110
300ms
4.8s
0111
350ms
5.6s
1000
400ms
6.4s
1001
450ms
7.2s
1010
500ms
8.0s
1011
550ms
8.8s
1100
600ms
9.6s
1101
650ms
10.4s
1110
700ms
11.2s
1111
750ms
12.0s
CDP1020
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