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參數(shù)資料
| 型號： | CDP1020 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | SMBus/I2C ACPI Dual Device Bay Controller |
| 中文描述： | I2C BUS CONTROLLER, PDSO28 |
| 封裝： | PLASTIC, MS-013AE, SOIC-28 |
| 文件頁數(shù)： | 5/23頁 |
| 文件大?。?/td> | 154K |
| 代理商： | CDP1020 |
2-422
Notational Conventions
The following conventions are used throughout this
document:
Hexadecimal numbers are denoted with a “$” symbol
preceding the number.
Binary numbers are represented with a “%” symbol
proceeding the number, or a “b” following.
Because of the large mix of active-low and active-high
signals used in connection with the CDP1020, the terms
“asserted” and “de-asserted” will be used exclusively. An
active low signal is asserted when it is at a logic 0 and de-
asserted when it is at a logic 1 state. Conversely, an active
high signal is at a logic 1 state when asserted and at a
logic 0 state when de-asserted. The terms reset, clear,
and “l(fā)ow” can also mean logic 0; set or “high” can also
mean logic 1.
Active low signals are represented with an overline; active
high signals have no overline. For example, REMREQ0 is
active low, PWREN0 is active high.
There are many pins, signals, registers, and software bits
common to both Bay 0 and Bay 1; these names may
include the Bay number suffix (0 or 1), an “x” to represent
either, or no suffix at all. For example, PWREN, PWREN0,
or PWRENx may each be used to describe output pin(s).
SCK
SDA
STOP
START
START
t
HD:STA
t
LOW
t
HIGH
t
SU:STO
STOP
t
HD:DAT
t
SU:DAT
t
SU:STA
t
HD:STA
FIGURE 1. CONTROL TIMING
t
BUF
Control Timing
V
DD
= 3.3V
±
10%, T
A
= 0
o
C to 85
o
C
PARAMETER
SYMBOL
MIN
MAX
UNITS
Frequency Of Operation (4.0MHz nominal) (CLK Pin)
f
CLK
t
RSUS
t
RL
t
DB
2.0
4.5
MHz
Suspend Recovery Start-up Time
RESET
Pulse Width (RESET Pin)
0.9
1
ms
6
-
t
OSC
ms
Input Debounce Time (1394PRx, USBPRx, REMREQx, SECUREx Pins)
50
-
SMBus
SCK and SDA Pins
SCK Frequency
f
SMB
t
BUF
t
HD:STA
t
SU:STA
t
SU:STO
t
HD:DAT
t
SU:DAT
t
TIMEOUT
t
LOW
t
HIGH
t
LOW:SEXT
t
LOW:MEXT
t
F
t
R
10
100
kHz
SMBus Free Time
4.7
-
μ
s
μ
s
μ
s
μ
s
Hold Time After (Repeated) Start Condition
4.0
-
Repeated Start Condition Setup Time
4.7
-
Stop Condition Setup Time
4.0
-
Data Hold Time
300
-
ns
Data Setup Time
250
-
ns
SCK Time-out Period
25
35
ms
SCK Low Period
4.7
-
μ
s
μ
s
SCK High Period
4.0
50
Slave SCK Extend Period (cumulative)
-
25
ms
Master SCK Extend Period (cumulative)
-
10
ms
SCK/SMBDAT Fall Time
-
300
ns
SCK/SMBDAT Rise Time
-
1000
ns
CDP1020
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CDP1020M | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CDP1020M WAF | 制造商:Intersil Corporation 功能描述: |
| CD-P12 | 制造商:SMC Corporation of America 功能描述:SWITCH PROTECTOR 24VDC |
| CDP1582EX | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CDP1802A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 8-Bit Microprocessors |
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