參數(shù)資料
型號: CDB4265
廠商: Cirrus Logic Inc
文件頁數(shù): 31/46頁
文件大小: 0K
描述: BOARD EVAL FOR CS4265 CODEC
標準包裝: 1
主要目的: 音頻編解碼器
嵌入式:
已用 IC / 零件: CS4265
主要屬性: 立體聲 24 位 192 kHz 采樣率
次要屬性: 圖形用戶界面,S/PDIF/ I2S / I2C / SPI 接口
已供物品: 板,纜線,CD
產(chǎn)品目錄頁面: 754 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: CS4265-DNZR-ND - IC CODEC 24BIT 104DB 32-QFN
CS4265-DNZ-ND - IC CODEC 24BIT 104DB 32-QFN
598-1039-ND - IC CODEC 24BIT 104DB 32QFN
其它名稱: 598-1001
DS657F3
37
CS4265
6.2.4
Power-Down DAC (Bit 1)
Function:
The DAC pair will remain in a reset state whenever this bit is set.
6.2.5
Power-Down Device (Bit 0)
Function:
The device will enter a low-power state whenever this bit is set. The power-down bit is set by default and
must be cleared before normal operation can occur. The contents of the control registers are retained
when the device is in power-down.
6.3
DAC Control - Address 03h
6.3.1
DAC Digital Interface Format (Bits 5:4)
Function:
The required relationship between LRCK, SCLK and SDIN for the DAC is defined by the DAC Digital In-
terface Format and the options are detailed in Table 7 and Figures 5-7.
6.3.2
Mute DAC (Bit 2)
Function:
The DAC outputs will mute and the MUTEC pin will become active when this bit is set. Though this bit is
active high, it should be noted that the MUTEC pin is active low. The common mode voltage on the outputs
will be retained when this bit is set. The muting function is effected, similar to attenuation changes, by the
DACSoft and DACZero bits in the DAC Control 2 register.
7
65
432
10
Reserved
DAC_DIF1
DAC_DIF0
Reserved
MuteDAC
DeEmph
Reserved
DAC_DIF1 DAC_DIF0
Description
Format
Figure
0
Left Justified, up to 24-bit data (default)
0
0
1
IS, up to 24-bit data
1
1
0
Right-Justified, 16-bit Data
2
1
Right-Justified, 24-bit Data
3
Table 7. DAC Digital Interface Formats
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