參數(shù)資料
型號: CDB4265
廠商: Cirrus Logic Inc
文件頁數(shù): 24/46頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR CS4265 CODEC
標準包裝: 1
主要目的: 音頻編解碼器
嵌入式:
已用 IC / 零件: CS4265
主要屬性: 立體聲 24 位 192 kHz 采樣率
次要屬性: 圖形用戶界面,S/PDIF/ I2S / I2C / SPI 接口
已供物品: 板,纜線,CD
產品目錄頁面: 754 (CN2011-ZH PDF)
相關產品: CS4265-DNZR-ND - IC CODEC 24BIT 104DB 32-QFN
CS4265-DNZ-ND - IC CODEC 24BIT 104DB 32-QFN
598-1039-ND - IC CODEC 24BIT 104DB 32QFN
其它名稱: 598-1001
30
DS657F3
CS4265
4.11
Mute Control
The MUTEC pin becomes active during power-up initialization, reset, muting, if the MCLK to LRCK ratio is
incorrect, and during power-down. The MUTEC pin is intended to be used as control for an external mute
circuit in order to add off-chip mute capability.
Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute min-
imum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer
to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit. The
MUTEC pin is an active-low CMOS driver. See Figure 14 for a suggested active-low mute circuit.
4.12
AES3 Transmitter
The CS4265 includes an IEC60958-3 digital audio transmitter. A comprehensive buffering scheme provides
write access to the channel status data. This buffering scheme is described in the “Channel Status Buffer
The IEC60958-3 transmitter encodes and transmits audio and digital data according to the IEC60958-3
(S/PDIF) interface standard. The transmitter receives audio data from the input pin TXSDIN and control
clocks from the PCM Serial Interface. Audio and control data are multiplexed together and bi-phase mark
encoded. The resulting bit stream is driven from the output pin TXOUT to an output connector either directly
or through a transformer. The transmitter is clocked from the clock input pin MCLK.
The channel status (C) bits in the transmitted data stream are taken from storage areas within the CS4265.
The user can manually access the internal storage of the CS4265 to configure the transmitted channel sta-
tus data. The “Channel Status Buffer Management” section describes the method of manually accessing
the storage areas. The CS4265 transmits all zeros in the user (U) data fields.
4.12.1
TxOut Driver
The line driver is a low skew, low impedance, single-ended output capable of driving cables directly. The
driver is set to ground during reset (RESET = LOW), when no transmit clock is provided, and optionally
LPF
+V
EE
-V
EE
560
Audio
Out
2 k
10 k
-VEE
+VA
MMUN2111LT1
AOUT
MUTEC
AC
Couple
47 k
Figure 14. Suggested Active-Low Mute Circuit
CS4265
相關PDF資料
PDF描述
5070014034 HEAT SHRINK TUBING
H3CKH-6018G IDC CABLE - HKC60H/AE60G/HPK60H
6278873-9 C/A 50.125UM RIS MTRJ 9M1
UPA1E182MHD1TO CAP ALUM 1800UF 25V 20% RADIAL
5070012033 HEAT SHRINK TUBING
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