參數(shù)資料
型號(hào)： CD40103BMS
廠商： Intersil Corporation
元件分類： 通用總線功能
英文描述： CMOS 8-Stage Presettable Synchronous Down Counters(CMOS 8級(jí)可預(yù)置同步減計(jì)數(shù)器)
中文描述： 的CMOS 8級(jí)可預(yù)置計(jì)數(shù)器同步跌的CMOS（8級(jí)可預(yù)置同步減計(jì)數(shù)器）
文件頁數(shù)： 2/13頁
文件大?。?/td> 166K
代理商： CD40103BMS
7-1295
Specifications CD40102BMS, CD40103BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input
. . . . . . . . . . . . . . . . . . . . . . . .±
10mA
Operating Temperature Range. . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Package Types D, F, K, H
Storage Temperature Range (TSTG). . . . . . . . . . . -65
o
C to +150
o
C
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265
o
C
At Distance 1/16
±
1/32 Inch (1.59mm
±
0.79mm) from case for
10s Maximum
Reliability Information
Thermal Resistance
Ceramic DIP Package . . . . . . . . . . . . .
Flatpack Package . . . . . . . . . . . . . . . .
Maximum Package Power Dissipation (PD) at +125
o
C
For T
A
= -55
o
C to +100
o
C (Package Type D, F, K) . . . . . . 500mW
For T
A
= +100
o
C to +125
o
C (Package Type D, F, K). . . . . .Derate
θ
ja
θ
jc
80
o
C/W
70
o
C/W
20
o
C/W
20
o
C/W
Linearity at 12mW/
o
C to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For T
A
= Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175
o
C
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS
(NOTE 1)
GROUP A
SUBGROUPS
TEMPERATURE
+25
o
C
+125
o
C
-55
o
C
+25
o
C
+125
o
C
-55
o
C
+25
o
C
+125
o
C
-55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C 14.95
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+125
o
C
-55
o
C
+25
o
C, +125
o
C, -55
o
C
LIMITS
UNITS
MIN
MAX
Supply Current
IDD
VDD = 20V, VIN = VDD or GND
1
-
10
μ
A
2
-
1000
μ
A
VDD = 18V, VIN = VDD or GND
3
-
10
μ
A
Input Leakage Current
IIL
VIN = VDD or GND
VDD = 20V
1
-100
-
nA
2
-1000
-
nA
VDD = 18V
3
-100
-
nA
Input Leakage Current
IIH
VIN = VDD or GND
VDD = 20V
1
-
100
nA
2
-
1000
nA
VDD = 18V
3
-
100
nA
Output Voltage
VOL15
VDD = 15V, No Load
1, 2, 3
-
50
mV
Output Voltage
VOH15
VDD = 15V, No Load (Note 3)
1, 2, 3
-
V
Output Current (Sink)
IOL5
VDD = 5V, VOUT = 0.4V
1
0.53
-
mA
Output Current (Sink)
IOL10
VDD = 10V, VOUT = 0.5V
1
1.4
-
mA
Output Current (Sink)
IOL15
VDD = 15V, VOUT = 1.5V
1
3.5
-
mA
Output Current (Source)
IOH5A
VDD = 5V, VOUT = 4.6V
1
-
-0.53
mA
Output Current (Source)
IOH5B
VDD = 5V, VOUT = 2.5V
1
-
-1.8
mA
Output Current (Source)
IOH10
VDD = 10V, VOUT = 9.5V
1
-
-1.4
mA
Output Current (Source)
IOH15
VDD = 15V, VOUT = 13.5V
1
-
-3.5
mA
N Threshold Voltage
VNTH
VDD = 10V, ISS = -10
μ
A
1
-2.8
-0.7
V
P Threshold Voltage
VPTH
VSS = 0V, IDD = 10
μ
A
1
0.7
2.8
V
Functional
F
VDD = 2.8V, VIN = VDD or GND
7
VOH >
VDD/2
VOL <
VDD/2
V
VDD = 20V, VIN = VDD or GND
7
VDD = 18V, VIN = VDD or GND
8A
VDD = 3V, VIN = VDD or GND
8B
Input Voltage Low
(Note 2)
VIL
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
-
1.5
V
Input Voltage High
(Note 2)
VIH
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
3.5
-
V
Input Voltage Low
(Note 2)
VIL
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
-
4
V
Input Voltage High
(Note 2)
VIH
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
11
-
V
NOTES: 1. All voltages referenced to device GND, 100% testing being
implemented.
2. Go/No Go test with limits applied to inputs.
3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.
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