參數(shù)資料
型號: CD40103BMS
廠商: Intersil Corporation
元件分類: 通用總線功能
英文描述: CMOS 8-Stage Presettable Synchronous Down Counters(CMOS 8級可預(yù)置同步減計數(shù)器)
中文描述: 的CMOS 8級可預(yù)置計數(shù)器同步跌的CMOS(8級可預(yù)置同步減計數(shù)器)
文件頁數(shù): 12/13頁
文件大?。?/td> 166K
代理商: CD40103BMS
7-1305
CD40102BMS, CD40103BMS
FIGURE 13. DIVIDE-BY- “N” COUNTER
FIGURE 14. PROGRAMMABLE TIMER
FIGURE 15. MICROPROCESSOR INTERRUPT TIMER
FIGURE 16. SYNCHRONOUS CASCADING
FIGURE 17. RIPPLE CASCADING
J0
J1
J2
J3
J4
J5
J6
J7
N
CO/ZD
CI/CE
SPE
APE
CLR
CLOCK
VDD
VSS
fOUT =
fIN
(N + 1)
fIN
J0
J1
J2
J3
J4
J5
J6
J7
N
CO/ZD
CI/CE
SPE
APE
CLR
CLOCK
VDD
VSS
fIN
TIME-OUT
COUNT DOWN
PRESET
J0
J1
J2
J3
J4
J5
J6
J7
FROM
MICROPROCESSOR
DATA BUS
CO/ZD
CI/CE
SPE
APE
CLR
CLOCK
VDD
VSS
TO
MICROPROCESSOR
INTERRUPT LINE
EXT
OSC
PRESET TIMER
(I/O COMMAND)
CLOCK
ENABLE
INPUT
CLOCK
CI/CE
CO/ZD
CLOCK
CI/CE
CO/ZD
CLOCK
CI/CE
CO/ZD
CLOCK
CD4071BMS
*
CASCADED
OUTPUT
*
An output spike (160ns at VDD = 5V) occurs whenever two or more devices are cascaded in the
parallel-clocked mode because the clock-to-carry out delay is greater than the carry-in-to-carry
out delay. This spike is eliminated by gating the output of the last device with the clock as shown.
CLOCK
ENABLE
INPUT
CLOCK
CI/CE
CO/ZD
CLOCK
CI/CE
CO/ZD
CLOCK
CI/CE
CO/ZD
CLOCK
CASCADED
OUTPUT
VSS
VSS
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