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參數(shù)資料
| 型號： | CD40103BMS |
| 廠商： | Intersil Corporation |
| 元件分類： | 通用總線功能 |
| 英文描述： | CMOS 8-Stage Presettable Synchronous Down Counters(CMOS 8級可預(yù)置同步減計(jì)數(shù)器) |
| 中文描述： | 的CMOS 8級可預(yù)置計(jì)數(shù)器同步跌的CMOS（8級可預(yù)置同步減計(jì)數(shù)器） |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 166K |
| 代理商： | CD40103BMS |
7-1294
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
CD40102BMS
CD40103BMS
CMOS 8-Stage Presettable
Synchronous Down Counters
Description
CD40102BMS and CD40103BMS consist of an 8-stage syn-
chronous down counter with a single output which is active
when the internal count is zero. The CD40102BMS is config-
ured as two cascaded 4-bit BCD counters, and the
CD40103BMS contains a single 8-bit binary counter. Each
type has control inputs for enabling or disabling the clock, for
clearing the counter to its maximum count, and for presetting
the counter either synchronously or asynchronously. All con-
trol inputs and the CARRY-OUT/ZERO-DETECT output are
active-low logic.
In normal operation, the counter is decremented by one
count on each positive transition of the CLOCK. Counting is
inhibited when the CARRY-IN/COUNTER ENABLE (CI/CE)
inputs is high. The CARRY-OUT/ZERO-DETECT (CO/ZD)
output goes low when the count reaches zero if the CI/CE
input is low, and remains low for one full clock period.
When the SYNCHRONOUS PRESET-ENABLE (SPE) input
is low, data at the JAM input is clocked into the counter on
the next positive clock transition regardless of the state of
the CI/CE input. When the ASYNCHRONOUS PRESET-
ENABLE (APE) input is low, data at the JAM inputs is asyn-
chronously forced into the counter regardless of the state of
the SPE, CI/CE, or CLOCK inputs. JAM inputs J0-J7 repre-
sent two 4-bit BCD words for the CD40102BMS and a single
8-bit binary word for the CD40103BMS.
When the CLEAR (CLR) input is low, the counter is asyn-
chronously cleared to its maximum count (99
10
for the
CD40102BMS and 255
10
for the CD40103BMS) regardless
of the state of any other input. The precedence relationship
between control inputs is indicated in the truth table.
If all control inputs except CI/CE are high at the time of zero
count, the counters will jump to the maximum count, giving a
counting sequence of 100 or 256 clock pulses long.
This causes the CO/ZD output to go low to enable the clock
on each succeeding clock pulse.
The CD40102BMS and CD40103BMS may be cascaded
using the CI/CE input and the CO/ZD output, in either a syn-
chronous or ripple mode as shown in Figures 16 and 17.
The CD40102MS and CD40103BMS are supplied in these
16-lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
*CD40102B Only
*H4W
*H1L
H6W
CD40130B Only
H4X
H1F
Features
High Voltage Type (20V Rating)
CD40102BMS: 2-Decade BCD Type
CD40103BMS: 8-Bit Binary Type
Synchronous or Asynchronous Preset
Medium Speed Operation
- fCL = 3.6MHz (Typ) at 10V
Cascadable
100% Tested for Quiescent Current at 20V
Maximum Input Current of 1
μ
A at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25
o
C
Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
Standardized Symmetrical Output Characteristics
5V, 10V and 15V Parametric Ratings
Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
Divide-By- “N” Counters
Programmable Times
Interrupt Timers
Cycle/Program Counter
Pinout
CD40102BMS, CD40130BMS
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
CLOCK
CLEAR
CARRY IN/
J0
J1
J2
VSS
J3
VDD
SYNCHRONOUS
PRESET ENABLE
CARRY OUT/
ZERO DETECT
J7
J6
J5
J4
ASYNCHRONOUS
PRESET ENABLE
COUNTER ENABLE
File Number
3351
December 1992
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| CD40103BNSR | 功能描述:計(jì)數(shù)器 IC CMOS 8-St Preset 8B Binary Synch RoHS:否 制造商:NXP Semiconductors 計(jì)數(shù)器類型:Binary Counters 邏輯系列:74LV 位數(shù):10 計(jì)數(shù)法: 計(jì)數(shù)順序: 工作電源電壓:1 V to 5.5 V 工作溫度范圍:- 40 C to + 125 C 封裝 / 箱體:SOT-109 封裝:Reel |
| CD40103BNSRE4 | 功能描述:計(jì)數(shù)器 IC CMOS 8-St Preset 8B Binary Synch RoHS:否 制造商:NXP Semiconductors 計(jì)數(shù)器類型:Binary Counters 邏輯系列:74LV 位數(shù):10 計(jì)數(shù)法: 計(jì)數(shù)順序: 工作電源電壓:1 V to 5.5 V 工作溫度范圍:- 40 C to + 125 C 封裝 / 箱體:SOT-109 封裝:Reel |
| CD40103BNSRG4 | 功能描述:計(jì)數(shù)器 IC CMOS 8-St Preset 8B Binary Synch RoHS:否 制造商:NXP Semiconductors 計(jì)數(shù)器類型:Binary Counters 邏輯系列:74LV 位數(shù):10 計(jì)數(shù)法: 計(jì)數(shù)順序: 工作電源電壓:1 V to 5.5 V 工作溫度范圍:- 40 C to + 125 C 封裝 / 箱體:SOT-109 封裝:Reel |
| CD40103BPW | 功能描述:計(jì)數(shù)器 IC CMOS 8-St Preset 8B Binary Synch RoHS:否 制造商:NXP Semiconductors 計(jì)數(shù)器類型:Binary Counters 邏輯系列:74LV 位數(shù):10 計(jì)數(shù)法: 計(jì)數(shù)順序: 工作電源電壓:1 V to 5.5 V 工作溫度范圍:- 40 C to + 125 C 封裝 / 箱體:SOT-109 封裝:Reel |
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