參數(shù)資料
型號: C8051F300DK
廠商: Silicon Laboratories Inc
文件頁數(shù): 22/178頁
文件大小: 0K
描述: DEV KIT F300/301/302/303/304/305
標準包裝: 1
類型: MCU
適用于相關產(chǎn)品: Silicon Laboratories C8051 F300/001/002
所含物品: 評估板,電源,USB 線纜,適配器和文檔
產(chǎn)品目錄頁面: 626 (CN2011-ZH PDF)
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其它名稱: 336-1246
C8051F300/1/2/3/4/5
118
Rev. 2.9
SFR Definition 13.1. SMB0CF: SMBus Clock/Configuration
Bit7:
ENSMB: SMBus Enable.
This bit enables/disables the SMBus interface. When enabled, the interface constantly mon-
itors the SDA and SCL pins.
0: SMBus interface disabled.
1: SMBus interface enabled.
Bit6:
INH: SMBus Slave Inhibit.
When this bit is set to logic 1, the SMBus does not generate an interrupt when slave events
occur. This effectively removes the SMBus slave from the bus. Master Mode interrupts are
not affected.
0: SMBus Slave Mode enabled.
1: SMBus Slave Mode inhibited.
Bit5:
BUSY: SMBus Busy Indicator.
This bit is set to logic 1 by hardware when a transfer is in progress. It is cleared to logic 0
when a STOP or free timeout is sensed.
Bit4:
EXTHOLD: SMBus Setup and Hold Time Extension Enable.
This bit controls the SDA setup and hold times according to Table 13.2.
0: SDA Extended Setup and Hold Times disabled.
1: SDA Extended Setup and Hold Times enabled.
Bit3:
SMBTOE: SMBus SCL Timeout Detection Enable.
This bit enables SCL low timeout detection. If set to logic 1, the SMBus forces Timer 2 to
reload while SCL is high and allows Timer 2 to count when SCL goes low. If Timer 2 is con-
figured in split mode (T2SPLIT is set), only the high byte of Timer 2 is held in reload while
SCL is high. Timer 2 should be programmed to generate interrupts at 25 ms, and the Timer
2 interrupt service routine should reset SMBus communication.
Bit2:
SMBFTE: SMBus Free Timeout Detection Enable.
When this bit is set to logic 1, the bus will be considered free if SCL and SDA remain high for
more than 10 SMBus clock source periods.
Bits1–0: SMBCS1-SMBCS0: SMBus Clock Source Selection.
These two bits select the SMBus clock source, which is used to generate the SMBus bit
rate. The selected device should be configured according to Equation 13.1.
R/W
R
R/W
Reset Value
ENSMB
INH
BUSY
EXTHOLD SMBTOE SMBFTE SMBCS1 SMBCS0 00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xC1
SMBCS1
SMBCS0
SMBus Clock Source
0
Timer 0 Overflow
0
1
Timer 1 Overflow
1
0
Timer 2 High Byte Overflow
1
Timer 2 Low Byte Overflow
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