參數(shù)資料
型號: C8051F300DK
廠商: Silicon Laboratories Inc
文件頁數(shù): 126/178頁
文件大小: 0K
描述: DEV KIT F300/301/302/303/304/305
標準包裝: 1
類型: MCU
適用于相關(guān)產(chǎn)品: Silicon Laboratories C8051 F300/001/002
所含物品: 評估板,電源,USB 線纜,適配器和文檔
產(chǎn)品目錄頁面: 626 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: 336-1535-5-ND - IC 8051 MCU 8K FLASH 14-SOIC
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C8051F001-GQR-ND - IC 8051 MCU 32K FLASH 48TQFP
336-1245-ND - IC 8051 MCU 8K FLASH 11QFN
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其它名稱: 336-1246
Rev. 2.9
51
C8051F300/1/2/3/4/5
7.
Comparator0
C8051F300/1/2/3/4/5 devices include an on-chip programmable voltage comparator, which is shown in
Figure 7.1. Comparator0 offers programmable response time and hysteresis, an analog input multiplexer,
and two outputs that are optionally available at the Port pins: a synchronous “l(fā)atched” output (CP0), or an
asynchronous “raw” output (CP0A). The asynchronous CP0A signal is available even when the system
clock is not active. This allows Comparator0 to operate and generate an output with the device in STOP
mode. When assigned to a Port pin, the Comparator0 output may be configured as open drain or push-pull
(see Section “12.2. Port I/O Initialization” on page 106). Comparator0 may also be used as a reset
The inputs for Comparator0 are selected in the CPT0MX register (SFR Definition 7.2). The CMX0P1-
CMX0P0 bits select the Comparator0 positive input; the CMX0N1-CMX0N0 bits select the Comparator0
negative input.
Important Note About Comparator Inputs: The Port pins selected as comparator inputs should be con-
figured as analog inputs in their associated Port configuration register, and configured to be skipped by the
Crossbar (for details on Port configuration, see Section “12.3. General Purpose Port I/O” on page 108).
VDD
CPT0C
N
Reset
Decision
Tree
+
-
Crossbar
Interrupt
Logic
Q
SET
CLR
D
Q
SET
CLR
D
(SYNCHRONIZER)
GND
CP0 +
P0.0
P0.2
P0.4
P0.6
CP0 -
P0.1
P0.3
P0.5
P0.7
CP0EN
CP0OUT
CP0RIF
CP0FIF
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0
CP
T
0
M
X CMX0N1
CMX0N0
CMX0P1
CMX0P0
CP
T
0
M
D
CP0MD1
CP0MD0
CP0
Rising-edge
Interrupt Flag
CP0
Falling-edge
Interrupt Flag
CP0
CP0A
Figure 7.1. Comparator0 Functional Block Diagram
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參數(shù)描述
C8051F300DK-A 功能描述:DEV KIT FOR F300/301/302/304/305 RoHS:否 類別:編程器,開發(fā)系統(tǒng) >> 過時/停產(chǎn)零件編號 系列:- 標準包裝:1 系列:- 類型:MCU 適用于相關(guān)產(chǎn)品:Freescale MC68HC908LJ/LK(80-QFP ZIF 插口) 所含物品:面板、纜線、軟件、數(shù)據(jù)表和用戶手冊 其它名稱:520-1035
C8051F300DK-B 功能描述:DEV KIT FOR F300/301/302/304/305 RoHS:否 類別:編程器,開發(fā)系統(tǒng) >> 過時/停產(chǎn)零件編號 系列:- 標準包裝:1 系列:- 類型:MCU 適用于相關(guān)產(chǎn)品:Freescale MC68HC908LJ/LK(80-QFP ZIF 插口) 所含物品:面板、纜線、軟件、數(shù)據(jù)表和用戶手冊 其它名稱:520-1035
C8051F300DK-E 功能描述:DEV KIT FOR F300/301/302/304/305 RoHS:否 類別:編程器,開發(fā)系統(tǒng) >> 過時/停產(chǎn)零件編號 系列:- 標準包裝:1 系列:- 類型:MCU 適用于相關(guān)產(chǎn)品:Freescale MC68HC908LJ/LK(80-QFP ZIF 插口) 所含物品:面板、纜線、軟件、數(shù)據(jù)表和用戶手冊 其它名稱:520-1035
C8051F300DK-G 功能描述:8位微控制器 -MCU MCU DEVELOPMENT KIT W/ GLOBAL POWER SPLY RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
C8051F300DK-H 功能描述:DEV KIT FOR F300/301/302/304/305 RoHS:否 類別:編程器,開發(fā)系統(tǒng) >> 過時/停產(chǎn)零件編號 系列:- 標準包裝:1 系列:- 類型:MCU 適用于相關(guān)產(chǎn)品:Freescale MC68HC908LJ/LK(80-QFP ZIF 插口) 所含物品:面板、纜線、軟件、數(shù)據(jù)表和用戶手冊 其它名稱:520-1035