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參數(shù)資料
| 型號(hào)： | C8051F006 |
| 廠(chǎng)商： | Cygnal Technologies |
| 英文描述： | 25 MIPS,32k Flash,2.25k Ram,12bit ADC,48 Pin MCU(25 MIPS,32k 閃速存儲(chǔ)器,2.25k Ram,12位 ADC,48 腳 MCU) |
| 中文描述： | 25 MIPS的，32K閃存，2.25k羊，12位ADC，48引腳微控制器（25 MIPS的，32K的閃速存儲(chǔ)器，2.25k羊，12位ADC和48腳微控制器） |
| 文件頁(yè)數(shù)： | 5/170頁(yè) |
| 文件大?。?/td> | 1294K |
| 代理商： | C8051F006 |
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4.2001; Rev. 1.3
CYGNAL Integrated Products, Inc.
2001
Page 5
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
PRELIMINARY
Figure 15.6. P0: Port0 Register......................................................................................................................108
Figure 15.7. PRT0CF: Port0 Configuration Register.....................................................................................108
Figure 15.8. P1: Port1 Register......................................................................................................................109
Figure 15.9. PRT1CF: Port1 Configuration Register.....................................................................................109
Figure 15.10. PRT1IF: Port1 Interrupt Flag Register ....................................................................................109
Figure 15.11. P2: Port2 Register....................................................................................................................110
Figure 15.12. PRT2CF: Port2 Configuration Register...................................................................................110
Figure 15.13. P3: Port3 Register....................................................................................................................111
Figure 15.14. PRT3CF: Port3 Configuration Register...................................................................................111
Table 15.2. Port I/O DC Electrical Characteristics........................................................................................111
16. SMBus...............................................................................................................................112
Figure 16.1. SMBus Block Diagram..............................................................................................................112
Figure 16.2. Typical SMBus Configuration...................................................................................................113
16.1. Supporting Documents.........................................................................................................................113
16.2. Operation..............................................................................................................................................114
Figure 16.3. SMBus Transaction....................................................................................................................114
16.3. Arbitration............................................................................................................................................115
16.4. Clock Low Extension...........................................................................................................................115
16.5. Timeouts...............................................................................................................................................115
16.6. SMBus Special Function Registers......................................................................................................115
Figure 16.4. SMB0CN: SMBus Control Register...........................................................................................117
Figure 16.5. SMB0CR: SMBus Clock Rate Register.....................................................................................118
Figure 16.6. SMB0DAT: SMBus Data Register............................................................................................119
Figure 16.7. SMB0ADR: SMBus Address Register ......................................................................................119
Figure 16.8. SMB0STA: SMBus Status Register...........................................................................................120
Table 16.1. SMBus Status Codes...................................................................................................................121
17. SERIAL PERIPHERAL INTERFACE BUS................................................................122
Figure 17.1. SPI Block Diagram....................................................................................................................122
Figure 17.2. Typical SPI Interconnection ......................................................................................................123
17.1. Signal Descriptions ..............................................................................................................................123
17.2. Operation..............................................................................................................................................124
Figure 17.3. Full Duplex Operation...............................................................................................................124
17.3. Serial Clock Timing.............................................................................................................................125
Figure 17.4. Data/Clock Timing Diagram......................................................................................................125
17.4. SPI Special Function Registers ............................................................................................................126
Figure 17.5. SPI0CFG: SPI Configuration Register.......................................................................................126
Figure 17.6. SPI0CN: SPI Control Register...................................................................................................127
Figure 17.7. SPI0CKR: SPI Clock Rate Register...........................................................................................128
Figure 17.8. SPI0DAT: SPI Data Register.....................................................................................................128
18. UART................................................................................................................................129
Figure 18.1. UART Block Diagram...............................................................................................................129
18.1. UART Operational Modes...................................................................................................................130
Table 18.1. UART Modes..............................................................................................................................130
Figure 18.2. UART Mode 0 Interconnect......................................................................................................130
Figure 18.3. UART Mode 0 Timing Diagram................................................................................................130
Figure 18.4. UART Mode 1 Timing Diagram................................................................................................131
Figure 18.5. UART Modes 1, 2, and 3 Interconnect Diagram.......................................................................132
Figure 18.6. UART Modes 2 and 3 Timing Diagram ....................................................................................132
18.2. Multiprocessor Communications..........................................................................................................133
Figure 18.7. UART Multi-Processor Mode Interconnect Diagram................................................................133
Table 18.2. Oscillator Frequencies for Standard Baud Rates.........................................................................134
Figure 18.8. SBUF: Serial (UART) Data Buffer Register..............................................................................134
Figure 18.9. SCON: Serial Port Control Register ..........................................................................................135
19. TIMERS............................................................................................................................136
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| C8051F006-GQ | 功能描述:8位微控制器 -MCU 32KB 12ADC RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| C8051F006-GQR | 功能描述:8位微控制器 -MCU 32KB 12ADC 48Pin MCU Tape and Reel RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| C8051F006R | 功能描述:8位微控制器 -MCU C +-12Bit 48Pin RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| C8051F007 | 功能描述:8位微控制器 -MCU 32KB 12ADC RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| C8051F007-GQ | 功能描述:8位微控制器 -MCU 32KB 12ADC RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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