參數(shù)資料
型號： C8051F006
廠商： Cygnal Technologies
英文描述： 25 MIPS,32k Flash,2.25k Ram,12bit ADC,48 Pin MCU(25 MIPS,32k 閃速存儲器,2.25k Ram,12位 ADC,48 腳 MCU)
中文描述： 25 MIPS的，32K閃存，2.25k羊，12位ADC，48引腳微控制器（25 MIPS的，32K的閃速存儲器，2.25k羊，12位ADC和48腳微控制器）
文件頁數(shù)： 127/170頁
文件大?。?/td> 1294K
代理商： C8051F006
4.2001; Rev. 1.3
CYGNAL Integrated Products, Inc.
2001
Page 127
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
PRELIMINARY
Figure 17.6. SPI0CN: SPI Control Register
R/W
SPIF
Bit7
R/W
WCOL
Bit6
R/W
MODF
Bit5
R/W
R
R
R/W
MSTEN
Bit1
R/W
SPIEN
Bit0
Reset Value
00000000
SFR Address:
0xF8
RXOVRN
Bit4
TXBSY
Bit3
SLVSEL
Bit2
Bit7:
SPIF: SPI Interrupt Flag.
This bit is set to logic 1 by hardware at the end of a data transfer. If interrupts are enabled,
setting this bit causes the CPU to vector to the SPI0 interrupt service routine. This bit is not
automatically cleared by hardware. It must be cleared by software.
Bit6:
WCOL: Write Collision Flag.
This bit is set to logic 1 by hardware (and generates a SPI interrupt) to indicate a write to
the SPI data register was attempted while a data transfer was in progress. It is cleared by
software.
Bit5:
MODF: Mode Fault Flag.
This bit is set to logic 1 by hardware (and generates a SPI interrupt) when a master mode
collision is detected (NSS is low and MSTEN = 1). This bit is not automatically cleared by
hardware. It must be cleared by software.
Bit4:
RXOVRN: Receive Overrun Flag.
This bit is set to logic 1 by hardware (and generates a SPI interrupt) when the receive buffer
still holds unread data from a previous transfer and the last bit of the current transfer is
shifted into the SPI shift register. This bit is not automatically cleared by hardware. It must
be cleared by software.
Bit3:
TXBSY: Transmit Busy Flag.
This bit is set to logic 1 by hardware while a master mode transfer is in progress. It is
cleared by hardware at the end of the transfer.
Bit2:
SLVSEL: Slave Selected Flag.
This bit is set to logic 1 whenever the NSS pin is low indicating it is enabled as a slave. It
is cleared to logic 0 when NSS is high (slave disabled).
Bit1:
MSTEN: Master Mode Enable.
0: Disable master mode. Operate in slave mode.
1: Enable master mode. Operate as a master.
Bit0:
SPIEN: SPI Enable.
This bit enables/disables the SPI.
0: SPI disabled.
1: SPI enabled.
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PDF描述
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C8051F022 25 MIPS,64k Flash,4.25k Ram,10bit ADC,100 Pin MCU(25 MIPS,64k 閃速存儲器,4.25k Ram,10位 ADC,100 腳 MCU)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
C8051F006-GQ 功能描述:8位微控制器 -MCU 32KB 12ADC RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
C8051F006-GQR 功能描述:8位微控制器 -MCU 32KB 12ADC 48Pin MCU Tape and Reel RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
C8051F006R 功能描述:8位微控制器 -MCU C +-12Bit 48Pin RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
C8051F007 功能描述:8位微控制器 -MCU 32KB 12ADC RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
C8051F007-GQ 功能描述:8位微控制器 -MCU 32KB 12ADC RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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