參數(shù)資料
型號： C8051F005
廠商： Cygnal Technologies
英文描述： 25 MIPS,32k Flash,2.25k Ram,12bit ADC,64 Pin MCU(25 MIPS,32k 閃速存儲器,2.25k Ram,12位 ADC,64 腳 MCU)
中文描述： 25 MIPS的，32K閃存，2.25k羊，12位ADC，64引腳微控制器（25 MIPS的，32K的閃速存儲器，2.25k羊，12位ADC和64腳微控制器）
文件頁數(shù)： 77/170頁
文件大?。?/td> 1294K
代理商： C8051F005
4.2001; Rev. 1.3
CYGNAL Integrated Products, Inc.
2001
Page 77
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
PRELIMINARY
Table 10.4. Interrupt Summary
Interrupt Source
Interrupt
Vector
0x0000
0x0003
0x000B
0x0013
0x001B
0x0023
Priority
Order
Top
0
1
2
3
4
Interrupt-Pending Flag
Enable
Reset
External Interrupt 0 (/INT0)
Timer 0 Overflow
External Interrupt 1 (/INT1)
Timer 1 Overflow
Serial Port (UART)
None
IE0 (TCON.1)
TF0 (TCON.5)
IE1 (TCON.3)
TF1 (TCON.7)
RI (SCON.0)
TI (SCON.1)
TF2 (T2CON.7)
SPIF (SPI0STA.7)
SI (SMB0CN.3)
ADWINT (ADC0CN.2)
CF (PCA0CN.7)
CCFn (PCA0CN.n)
CP0FIF (CPT0CN.4)
CP0RIF (CPT0CN.3)
CP1FIF (CPT1CN.4)
CP1RIF (CPT1CN.3)
TF3 (TMR3CN.7)
ADCINT (ADC0CN.5)
IE4 (PRT1IF.4)
IE5 (PRT1IF.5)
IE6 (PRT1IF.6)
IE7 (PRT1IF.7)
None
XTLVLD (OSCXCN.7)
Always enabled
EX0 (IE.0)
ET0 (IE.1)
EX1 (IE.2)
ET1 (IE.3)
ES (IE.4)
Timer 2 Overflow (or EXF2)
Serial Peripheral Interface
SMBus Interface
ADC0 Window Comparison
Programmable Counter Array 0
0x002B
0x0033
0x003B
0x0043
0x004B
5
6
7
8
9
ET2 (IE.5)
ESPI0 (EIE1.0)
ESMB0 (EIE1.1)
EWADC0 (EIE1.2)
EPCA0 (EIE1.3)
Comparator 0 Falling Edge
Comparator 0 Rising Edge
Comparator 1 Falling Edge
Comparator 1 Rising Edge
Timer 3 Overflow
ADC0 End of Conversion
External Interrupt 4
External Interrupt 5
External Interrupt 6
External Interrupt 7
Unused Interrupt Location
External Crystal OSC Ready
0x0053
0x005B
0x0063
0x006B
0x0073
0x007B
0x0083
0x008B
0x0093
0x009B
0x00A3
0x00AB
10
11
12
13
14
15
16
17
18
19
20
21
ECP0F (EIE1.4)
ECP0R (EIE1.5)
ECP1F (EIE1.6)
ECP1R (EIE1.7)
ET3 (EIE2.0)
EADC0 (EIE2.1)
EX4 (EIE2.2)
EX5 (EIE2.3)
EX6 (EIE2.4)
EX7 (EIE2.5)
Reserved (EIE2.6)
EXVLD (EIE2.7)
10.4.3. Interrupt Priorities
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low priority
interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be
preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP-EIP2) used to configure its priority
level. Low priority is the default. If two interrupts are recognized simultaneously, the interrupt with the higher
priority is serviced first. If both interrupts have the same priority level, a fixed priority order is used to arbitrate.
10.4.4. Interrupt Latency
Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are sampled
and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5 system clock cycles:
1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the ISR. If an interrupt is pending
when a RETI is executed, a single instruction is executed before an LCALL is made to service the pending interrupt.
Therefore, the maximum response time for an interrupt (when no other interrupt is currently being serviced or the
new interrupt is of greater priority) occurs when the CPU is performing an RETI instruction followed by a DIV as
the next instruction. In this case, the response time is 18 system clock cycles: 1 clock cycle to detect the interrupt, 5
clock cycles to execute the RETI, 8 clock cycles to complete the DIV instruction and 4 clock cycles to execute the
LCALL to the ISR. If the CPU is executing an ISR for an interrupt with equal or higher priority, the new interrupt
will not be serviced until the current ISR completes, including the RETI and following instruction.
相關(guān)PDF資料
PDF描述
C8051F006 25 MIPS,32k Flash,2.25k Ram,12bit ADC,48 Pin MCU(25 MIPS,32k 閃速存儲器,2.25k Ram,12位 ADC,48 腳 MCU)
C8051F007 25 MIPS,32k Flash,2.25k Ram,12bit ADC,32 Pin MCU(25 MIPS,32k 閃速存儲器,2.25k Ram,12位 ADC,32 腳 MCU)
C8051F010 20 MIPS,32k Flash,256 Ram,10bit ADC,64 Pin MCU(20 MIPS,32k 閃速存儲器,256 Ram,10位 ADC,64 腳 MCU)
C8051F015 25 MIPS,32k Flash,2.25k Ram,10bit ADC,64 Pin MCU(25 MIPS,32k 閃速存儲器,2.25k Ram,10位 ADC,64 腳 MCU)
C8051F016 25 MIPS,32k Flash,2.25k Ram,10bit ADC,48 Pin MCU(25 MIPS,32k 閃速存儲器,2.25k Ram,10位 ADC,48 腳 MCU)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
C8051F005/0046 制造商:Silicon Laboratories Inc 功能描述:
C8051F005DK 功能描述:開發(fā)板和工具包 - 8051 MCU DEVELOPMENT KIT W/ US POWER SUPPLY RoHS:否 制造商:Silicon Labs 產(chǎn)品:Development Kits 工具用于評估:C8051F960, Si7005 核心: 接口類型:USB 工作電源電壓:
C8051F005DK-A 功能描述:DEV KIT FOR C8051F005/F006/F007 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 過時/停產(chǎn)零件編號 系列:- 標(biāo)準包裝:1 系列:- 類型:MCU 適用于相關(guān)產(chǎn)品:Freescale MC68HC908LJ/LK（80-QFP ZIF 插口） 所含物品:面板、纜線、軟件、數(shù)據(jù)表和用戶手冊 其它名稱:520-1035
C8051F005DK-B 功能描述:DEV KIT FOR C8051F005/F006/F007 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 過時/停產(chǎn)零件編號 系列:- 標(biāo)準包裝:1 系列:- 類型:MCU 適用于相關(guān)產(chǎn)品:Freescale MC68HC908LJ/LK（80-QFP ZIF 插口） 所含物品:面板、纜線、軟件、數(shù)據(jù)表和用戶手冊 其它名稱:520-1035
C8051F005DK-E 功能描述:DEV KIT FOR C8051F005/F006/F007 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 過時/停產(chǎn)零件編號 系列:- 標(biāo)準包裝:1 系列:- 類型:MCU 適用于相關(guān)產(chǎn)品:Freescale MC68HC908LJ/LK（80-QFP ZIF 插口） 所含物品:面板、纜線、軟件、數(shù)據(jù)表和用戶手冊 其它名稱:520-1035
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