參數(shù)資料
型號： C8051F005
廠商： Cygnal Technologies
英文描述： 25 MIPS,32k Flash,2.25k Ram,12bit ADC,64 Pin MCU(25 MIPS,32k 閃速存儲器,2.25k Ram,12位 ADC,64 腳 MCU)
中文描述： 25 MIPS的，32K閃存，2.25k羊，12位ADC，64引腳微控制器（25 MIPS的，32K的閃速存儲器，2.25k羊，12位ADC和64腳微控制器）
文件頁數(shù)： 133/170頁
文件大?。?/td> 1294K
代理商： C8051F005
4.2001; Rev. 1.3
CYGNAL Integrated Products, Inc.
2001
Page 133
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
PRELIMINARY
18.2.
Modes 2 and 3 support multiprocessor communication between a master processor and one or more slave processors
by special use of the ninth data bit. When a master processor wants to transmit to one or more slaves, it first sends an
address byte to select the target(s). An address byte differs from a data byte in that its ninth bit is logic 1; in a data
byte, the ninth bit is always set to logic 0.
Setting the SM2 bit (SCON.5) of a slave processor configures its UART such that when a stop bit is received, the
UART will generate an interrupt only if the ninth bit is logic one (RB8 = 1) signifying an address byte has been
received. In the UART’s interrupt handler, software will compare the received address with the slave’s own
assigned 8-bit address. If the addresses match, the slave will clear its SM2 bit to enable interrupts on the reception of
the following data byte(s). Slaves that weren’t addressed leave their SM2 bits set and do not generate interrupts on
the reception of the following data bytes, thereby ignoring the data. Once the entire message is received, the
addressed slave resets its SM2 bit to ignore all transmissions until it receives the next address byte.
Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple slaves,
thereby enabling “broadcast” transmissions to more than one slave simultaneously. The master processor can be
configured to receive all transmissions or a protocol can be implemented such that the master/slave role is
temporarily reversed to enable half-duplex transmission between the original master and slave(s).
Multiprocessor Communications
Figure 18.7. UART Multi-Processor Mode Interconnect Diagram
Master
Device
Slave
Device
TX
RX
RX
TX
Slave
Device
RX
TX
Slave
Device
RX
TX
VDD
相關(guān)PDF資料
PDF描述
C8051F006 25 MIPS,32k Flash,2.25k Ram,12bit ADC,48 Pin MCU(25 MIPS,32k 閃速存儲器,2.25k Ram,12位 ADC,48 腳 MCU)
C8051F007 25 MIPS,32k Flash,2.25k Ram,12bit ADC,32 Pin MCU(25 MIPS,32k 閃速存儲器,2.25k Ram,12位 ADC,32 腳 MCU)
C8051F010 20 MIPS,32k Flash,256 Ram,10bit ADC,64 Pin MCU(20 MIPS,32k 閃速存儲器,256 Ram,10位 ADC,64 腳 MCU)
C8051F015 25 MIPS,32k Flash,2.25k Ram,10bit ADC,64 Pin MCU(25 MIPS,32k 閃速存儲器,2.25k Ram,10位 ADC,64 腳 MCU)
C8051F016 25 MIPS,32k Flash,2.25k Ram,10bit ADC,48 Pin MCU(25 MIPS,32k 閃速存儲器,2.25k Ram,10位 ADC,48 腳 MCU)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
C8051F005/0046 制造商:Silicon Laboratories Inc 功能描述:
C8051F005DK 功能描述:開發(fā)板和工具包 - 8051 MCU DEVELOPMENT KIT W/ US POWER SUPPLY RoHS:否 制造商:Silicon Labs 產(chǎn)品:Development Kits 工具用于評估:C8051F960, Si7005 核心: 接口類型:USB 工作電源電壓:
C8051F005DK-A 功能描述:DEV KIT FOR C8051F005/F006/F007 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 過時/停產(chǎn)零件編號 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:MCU 適用于相關(guān)產(chǎn)品:Freescale MC68HC908LJ/LK（80-QFP ZIF 插口） 所含物品:面板、纜線、軟件、數(shù)據(jù)表和用戶手冊 其它名稱:520-1035
C8051F005DK-B 功能描述:DEV KIT FOR C8051F005/F006/F007 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 過時/停產(chǎn)零件編號 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:MCU 適用于相關(guān)產(chǎn)品:Freescale MC68HC908LJ/LK（80-QFP ZIF 插口） 所含物品:面板、纜線、軟件、數(shù)據(jù)表和用戶手冊 其它名稱:520-1035
C8051F005DK-E 功能描述:DEV KIT FOR C8051F005/F006/F007 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 過時/停產(chǎn)零件編號 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:MCU 適用于相關(guān)產(chǎn)品:Freescale MC68HC908LJ/LK（80-QFP ZIF 插口） 所含物品:面板、纜線、軟件、數(shù)據(jù)表和用戶手冊 其它名稱:520-1035
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