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    參數(shù)資料
    型號(hào): BX80525U733256E
    廠商: INTEL CORP
    元件分類: 微控制器/微處理器
    英文描述: 32-BIT, 733 MHz, MICROPROCESSOR, XMA
    文件頁(yè)數(shù): 48/102頁(yè)
    文件大?。?/td> 878K
    代理商: BX80525U733256E
    Datasheet
    5
    Pentium III Processor for the SC242 at 450 MHz to 800 MHz
    Figures
    1
    Second Level (L2) Cache Implementation ........................................................... 7
    2
    AGTL+ Bus Topology .......................................................................................... 12
    3
    Stop Clock State Machine ................................................................................... 12
    4
    BSEL[1:0] Example for a 100 MHz System Design
    (100 MHz Processor Installed) ............................................................................20
    5
    BSEL[1:0] Example for a 100/133 MHz Capable System
    (100 MHz Processor Installed) ............................................................................21
    6
    BSEL[1:0] Example for a 100/133 MHz Capable System
    (133 MHz Processor Installed) ............................................................................21
    7
    BCLK, PICCLK, and TCK Generic Clock Waveform ........................................... 33
    8
    System Bus Valid Delay Timings ........................................................................ 33
    9
    System Bus Setup and Hold Timings.................................................................. 34
    10
    System Bus Reset and Configuration Timings.................................................... 34
    11
    Power-On Reset and Configuration Timings....................................................... 34
    12
    Test Timings (TAP Connection) .......................................................................... 35
    13
    Test Reset Timings ............................................................................................. 35
    14
    BCLK and PICCLK Generic Clock Waveform ..................................................... 36
    15
    Maximum Acceptable AGTL+ and Non-AGTL+ Overshoot/Undershoot
    Waveform ............................................................................................................42
    16
    Low to High AGTL+ and Non-AGTL+ Receiver Ringback Tolerance ................. 44
    17
    Signal Overshoot/Undershoot, Settling Limit, and Ringback 1............................ 44
    18
    S.E.C.Cartridge — 3-Dimensional View.............................................................. 45
    19
    S.E.C.Cartridge 2 — Substrate View .................................................................. 46
    20
    Processor Functional Die Layout (CPUID 068xh) ............................................... 47
    21
    S.E.C.C. Packaged Processor — Multiple Views................................................ 49
    22
    S.E.C.C. Packaged Processor — Extended Thermal Plate Side Dimensions .... 50
    23
    S.E.C.C. Packaged Processor — Bottom View Dimensions...............................50
    24
    S.E.C.C. Packaged Processor — Latch Arm, Extended Thermal Plate Lug,
    and Cover Lug Dimensions ................................................................................. 51
    25
    S.E.C.C. Packaged Processor — Latch Arm, Extended Thermal Plate,
    and Cover Detail Dimensions (Reference Dimensions Only).............................. 52
    26
    S.E.C.C. Packaged Processor — Extended Thermal Plate Attachment
    Detail Dimensions ...............................................................................................53
    27
    S.E.C.C. Packaged Processor — Extended Thermal Plate Attachment
    Detail Dimensions, Continued ............................................................................. 54
    28
    S.E.C.C. Packaged Processor Substrate — Edge Finger Contact
    Dimensions.......................................................................................................... 54
    29
    S.E.C.C. Packaged Processor Substrate — Edge Finger Contact
    Dimensions, Detail A ........................................................................................... 55
    30
    Intel Pentium III Processor Markings (S.E.C.C. Packaged Processor) ...........55
    31
    S.E.C.C.2 Packaged Processor — Multiple Views.............................................. 56
    32
    S.E.C.C.2 Packaged Processor Assembly — Primary View ...............................57
    33
    S.E.C.C.2 Packaged Processor Assembly — Cover View with Dimensions ...... 57
    34
    S.E.C.C.2 Packaged Processor Assembly — Heat Sink Attach Boss Section ... 58
    35
    S.E.C.C.2 Packaged Processor Assembly — Side View .................................... 58
    36
    Detail View of Cover in the Vicinity of the Substrate Attach Features................. 58
    37
    S.E.C.C.2 Packaged Processor Substrate — Edge Finger Contact
    Dimensions.......................................................................................................... 59
    38
    S.E.C.C.2 Packaged Processor Substrate — Edge Finger Contact
    Dimensions (Detail A).......................................................................................... 59
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