參數(shù)資料
型號(hào)： BX80525U733256E
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 733 MHz, MICROPROCESSOR, XMA
文件頁數(shù)： 29/102頁
文件大?。?/td> 878K
代理商： BX80525U733256E
32
Datasheet
Pentium III Processor for the SC242 at 450 MHz to 800 MHz
NOTE:
1. Contact your local Intel representative for the latest information on processor frequencies and/or frequency
multipliers.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processor frequencies.
2. These specifications are tested during manufacturing.
3. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 1.25 V at the processor core
pin. All AGTL+ signal timings (compatibility signals, etc.) are referenced at 1.00 V at the processor core pins.
4. Valid delay timings for these signals are specified into 25
to 1.5 V and with VREF at 1.0 V.
5. Valid delay timings for these signals are specified into 50
to 1.5 V and with VREF at 1.0 V.
6. A minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of TRDY#.
7. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously. For 2-way MP
systems, RESET# should be synchronous.
8. Specification is for a minimum 0.40 V swing.
9. Specification is for a maximum 1.0 V swing.
10.This should be measured after VCCCORE, VCCL2/VCC3.3, and BCLK become stable.
11. This specification applies to the Pentium III processor with a system bus frequency of 100 MHz
.
12.This specification applies to the Pentium III processor with a system bus frequency of 133 MHz
.
13.This specification applies to the Pentium III processor with CPUID=067xh.
14.This specification applies to the Pentium III processor with CPUID=068xh.
Table 13. Valid System Bus, Core Frequency, and Cache Bus Frequencies
1
Processor
Core Frequency (MHz)
BCLK Frequency (MHz)
Frequency Multiplier
L2 Cache (MHz)
450
450.00
100.00
9/2
225.00
500
500.00
100.00
5
250.00
533B
533.33
133.33
4
266.66
533EB
533.33
133.33
4
533.33
550
550.00
100.00
11/2
275.00
550E
550.00
100.00
11/2
550.00
600
600.00
100.00
6
300.00
600B
600.00
133.33
9/2
300.00
600E
600.00
100.00
6
600.00
600EB
600.00
133.33
9/2
600.00
650
650.00
100.00
13/2
650.00
667
666.67
133.33
5
666.67
700
700.00
100.00
7
700.00
733
733.33
133.33
11/2
733.33
750
750.00
100.00
15/2
750.00
800
800.00
100.00
8
800.00
800EB
800.00
133.33
6
800.00
Table 14. System Bus AC Specifications (AGTL+ Signal Group) at the
Processor Core Pins 1, 2, 3
T# Parameter
Min
Max
Unit
Figure
Notes
T7: AGTL+ Output Valid Delay
-0.20
-0.14
-0.10
3.15
2.20
2.70
ns
8
4, 10, 13
5, 11, 13
5, 11, 12, 14
T8: AGTL+ Input Setup Time
1.90
1.20
ns
9
6, 7, 8, 11, 13
6, 7, 8, 12, 13
6, 7, 8, 11, 12, 14
T9: AGTL+ Input Hold Time
0.85
0.58
0.80
ns
9
9, 11, 13
9, 12, 13
9, 11, 12, 14
T10: RESET# Pulse Width
1.00
ms
11
7, 10
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