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參數(shù)資料
| 型號： | BX80525U733256E |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 733 MHz, MICROPROCESSOR, XMA |
| 文件頁數(shù)： | 17/102頁 |
| 文件大?。?/td> | 878K |
| 代理商： | BX80525U733256E |
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Datasheet
21
Pentium III Processor for the SC242 at 450 MHz to 800 MHz
NOTES:
1. The BR0# pin is the only BREQ# signal that is bidirectional. The internal BREQ# signals are mapped onto
BR# pins after the agent ID is determined. See Section 7.0 for more information.
2. See Section 7.0 for information on the PWRGOOD signal.
3. See Section 7.0 for information on the SLP# signal.
4. See Section 7.0 for information on the THERMTRIP# signal.
5. These signals are specified for 2.5 V operation.
6. VCCCORE is the power supply for the processor core.
VCCL2/VCC3.3 is described in Section 2.3.
VID[4:0] is described in Section 2.6.
VTT is used to terminate the system bus and generate VREF on the processor substrate.
VSS is system ground.
TESTHI should be connected to 2.5 V with a 1 k
–10 k resistor.
VCC5 is not connected to the Pentium
III processor core. This supply is used for the test equipment and
tools.
SLOTOCC# is described in Section 7.0.
BSEL[1:0] is described in Section 2.8.2 and Section 7.0.
EMI pins are described in Section 7.0.
THERMDP, THERMDN are described in Section 7.0.
2.8.1
Asynchronous vs. Synchronous for System Bus Signals
All AGTL+ signals are synchronous to BCLK. All of the CMOS, Clock, APIC, and TAP signals
can be applied asynchronously to BCLK.
All APIC signals are synchronous to PICCLK. All TAP signals are synchronous to TCK.
2.8.2
System Bus Frequency Select Signal (BSEL0)
The BSEL[1:0] signals (BSEL0 is also known as 100/66#) are used to select the system bus
frequency for the Pentium III processor(s). Table 5 defines the possible combinations of the signals
and the frequency associated with each combination. The frequency is determined by the
processor(s), and frequency synthesizer. All system bus agents must operate at the same core and
system bus frequency in a 2-way MP Pentium III processor configuration. In a 2-way MP system
Table 4.
System Bus Signal Groups
Group Name
Signals
AGTL+ Input
BPRI#, BR1#, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY#
AGTL+ Output
PRDY#
AGTL+ I/O
A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#, BPM[1:0]#,
BR0#1, D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#, LOCK#, REQ[4:0]#, RP#
CMOS Input5
A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, PWRGOOD2,
SMI#, SLP#3, STPCLK#
CMOS Output5
FERR#, IERR#, THERMTRIP#4
System Bus Clock
BCLK
APIC Clock
PICCLK
APIC I/O5
PICD[1:0]
TAP Input5
TCK, TDI, TMS, TRST#
TAP Output5
TDO
Power/Other6
VCCCORE, VCCL2/VCC3.3, VCC5, VID[4:0], VTT, VSS, SLOTOCC#, THERMDP, THERMDN,
BSEL[1:0], EMI, TESTHI, Reserved
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