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參數(shù)資料
| 型號： | BS62LV2006STI55 |
| 廠商： | BRILLIANCE SEMICONDUCTOR, INC. |
| 英文描述： | Very Low Power CMOS SRAM 256K X 8 bit |
| 中文描述： | 非常低功耗CMOS SRAM 256K × 8位 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 361K |
| 代理商： | BS62LV2006STI55 |
BS62LV2006
R0201-BS62LV2006
Revision
May.
1.3
2006
4
n
LOW V
CC
DATA RETENTION WAVEFORM (2) (CE2 Controlled)
n
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels
Vcc / 0V
Input Rise and Fall Times
1V/ns
Input and Output Timing
Reference Level
0.5Vcc
t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
WHZ
C
L
= 5pF+1TTL
Output Load
Others
C
L
= 30pF+1TTL
1. Including jig and scope capacitance.
n
AC ELECTRICAL CHARACTERISTICS (T
A
= -40
O
C to +85
O
C)
READ CYCLE
JEDEC
PARAMETER
NAME
n
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
MAY CHANGE
FROM
“
H
”
TO
“
L
”
WILL BE CHANGE
FROM
“
H
”
TO
“
L
”
MAY CHANGE
FROM
“
L
”
TO
“
H
”
WILL BE CHANGE
FROM
“
L
”
TO
“
H
”
DON
’
T CARE
ANY CHANGE
PERMITTED
CHANGE :
STATE UNKNOW
DOES NOT
APPLY
CENTER LINE IS
HIGH INPEDANCE
“
OFF
”
STATE
CYCLE TIME : 55ns
(V
CC
= 3.0~5.5V)
MIN.
TYP.
CYCLE TIME : 70ns
(V
CC
= 2.7~5.5V)
MIN.
TYP.
PARANETER
NAME
DESCRIPTION
MAX.
MAX.
UNITS
t
AVAX
t
RC
Read Cycle Time
55
--
--
70
--
--
ns
t
AVQX
t
AA
Address Access Time
--
--
55
--
--
70
ns
t
E1LQV
t
ACS1
Chip Select Access Time
(CE1)
--
--
55
--
--
70
ns
t
E2HQV
t
ACS2
Chip Select Access Time
(CE2)
--
--
55
--
--
70
ns
t
GLQV
t
OE
Output Enable to Output Valid
--
--
30
--
--
35
ns
t
E1LQX
t
CLZ1
Chip Select to Output Low Z
(CE1)
10
--
--
10
--
--
ns
t
E2HQX
t
CLZ2
Chip Select to Output Low Z
(CE2)
10
--
--
10
--
--
ns
t
GLQX
t
OLZ
Output Enable to Output Low Z
5
--
--
5
--
--
ns
t
E1HQZ
t
CHZ1
Chip Select to Output High Z
(CE1)
--
--
30
--
--
35
ns
t
E2LQZ
t
CHZ2
Chip Select to Output High Z
(CE2)
--
--
30
--
--
35
ns
t
GHQZ
t
OHZ
Output Enable to Output High Z
--
--
25
--
--
30
ns
t
AVQX
t
OH
Data Hold from Address Change
10
--
--
10
--
--
ns
CE2
Data Retention Mode
V
CC
t
CDR
V
CC
t
R
V
IL
V
IL
V
CC
V
DR
≧
1.5V
CE2
≦
0.2V
C
L
(1)
1 TTL
Output
ALL INPUT PULSES
→
←
Rise Time :
1V/ns
90%
V
CC
GND
Fall Time :
1V/ns
90%
→
←
10%
10%
相關PDF資料 |
PDF描述 |
|---|---|
| BS62LV2006STI70 | Very Low Power CMOS SRAM 256K X 8 bit |
| BS62LV2006TC55 | Very Low Power CMOS SRAM 256K X 8 bit |
| BS62LV2006TC70 | Very Low Power CMOS SRAM 256K X 8 bit |
| BS62LV2006TI55 | Very Low Power CMOS SRAM 256K X 8 bit |
| BS62LV2006TI70 | Very Low Power CMOS SRAM 256K X 8 bit |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| BS62LV2006STI-55 | 制造商:BSI 制造商全稱:Brilliance Semiconductor 功能描述:Very Low Power/Voltage CMOS SRAM 256K X 8 bit |
| BS62LV2006STI70 | 制造商:BSI 制造商全稱:Brilliance Semiconductor 功能描述:Very Low Power CMOS SRAM 256K X 8 bit |
| BS62LV2006STI-70 | 制造商:BSI 制造商全稱:Brilliance Semiconductor 功能描述:Very Low Power/Voltage CMOS SRAM 256K X 8 bit |
| BS62LV2006STIG55 | 制造商:BSI 制造商全稱:Brilliance Semiconductor 功能描述:Very Low Power/Voltage CMOS SRAM 256K X 8 bit |
| BS62LV2006STIG70 | 制造商:BSI 制造商全稱:Brilliance Semiconductor 功能描述:Very Low Power CMOS SRAM 256K X 8 bit |
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